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Add RISC-V support #5030

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Add RISC-V support #5030

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11 changes: 11 additions & 0 deletions configure.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -496,6 +496,17 @@ IF(NOT CMAKE_CROSSCOMPILING AND NOT MSVC)
}
" HAVE_HMT_PRIORITY_INSTRUCTION)
ENDIF()

# Check for RISC-V Zihintpause
IF (processor MATCHES "riscv")
CHECK_C_SOURCE_COMPILES("
int main()
{
__asm__ __volatile__ (\"pause\");
return 0;
}
" HAVE_PAUSE_INSTRUCTION)
ENDIF()
ENDIF()

INCLUDE (CheckIncludeFileCXX)
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29 changes: 29 additions & 0 deletions storage/ndb/include/portlib/mt-asm.h
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Expand Up @@ -157,6 +157,35 @@ xcng(volatile unsigned * addr, int val)

#define cpu_pause() __asm__ __volatile__ ("yield")

#elif defined(__riscv)
#define NDB_HAVE_MB
#define NDB_HAVE_RMB
#define NDB_HAVE_WMB
#define NDB_HAVE_XCNG

#define mb() asm volatile ("fence iorw, iorw" ::: "memory")
#define rmb() asm volatile ("fence ir, ir" ::: "memory")
#define wmb() asm volatile ("fence ow, ow" ::: "memory")

static
inline
int
xcng(volatile unsigned * addr, int val)
{
int prev;
__asm__ __volatile__ (
"amoswap.d.aqrl %0, %2, %1\n"
: "=r" (prev), "+A" (*addr)
: "r" (val)
: "memory");
return prev;
}

#if defined(HAVE_PAUSE_INSTRUCTION)
#define NDB_HAVE_PAUSE
#define cpu_pause() asm volatile ("pause")
#endif

#else
#define NDB_NO_ASM "Unsupported architecture (gcc)"
#endif
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