Add RISC-V support #5030
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Add RISC-V support #5030
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hack3ric
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Added RISC-V memory barrier, `xchg` and `cpu_pause`. Upstream: percona/percona-server#5030
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Added RISC-V memory barrier, `xchg` and `cpu_pause`. Upstream: percona/percona-server#5030
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Adds various memory barrier methods:
mb(),rmb(),wmb()according to RISC-V unpriviledged specs section A.5xcng()from Linux kernel source codecpu_pause()using Zihintpause'spause, with checks included.See also percona/percona-xtrabackup#1443.