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Add AXIS Cache IP, FPGA code housekeeping, etc. #826

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Add AXIS Cache IP, FPGA code housekeeping, etc. #826

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@n-eiling n-eiling commented Oct 27, 2024 •
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  • Various fixes for FPGA use cases.
  • New IP driver axis_cache
  • cleans up config files
  • improves comments

I modified the cast hook so it also works for writes. I use this for the DPsim VILLASnode interface to convert between double and complex.

@n-eiling n-eiling marked this pull request as ready for review November 4, 2024 14:37
@n-eiling n-eiling requested a review from stv0g as a code owner November 4, 2024 14:37
@n-eiling n-eiling changed the title Improving FPGA communication Add AXIS Cache IP, FPGA code housekeeping, etc. Nov 4, 2024
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stv0g requested changes Nov 4, 2024
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stv0g commented Nov 5, 2024

Thanks for addressing the nits about the code-style. Unfortunately, I think the DCO check isnt happy anymore about it..

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n-eiling commented Nov 5, 2024

i used the wrong mail address in the github ui. didn't know this affects the DCO check :)

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Let's merge this and move the discussion to VILLASframework/documentation#89

n-eiling and others added 13 commits November 18, 2024 12:43
@n-eiling
fpga: Add driver for new register interface of axis cache IP
d0a7b88 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Add new Dino configuration register that allows triggering the …
a62a9e4 
…DAC before the time step to dino.cpp

Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Add axis_cache.cpp to CMakeLists.txt
63e498a 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Fix I2c causing an error when Dino FMC is not connected. We loo…
9d693fb 
…se the self check, but this is not really possible if there is no Dino FMC.

Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
hooks: Cast hook should also work for writes.
e8cf0f7 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Clean up dino.cpp
2f48f6d 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga/ips: add invalidate method to AxisCache and whitelist the IP in …
8e6ec16 
…hwdef-parse.py

Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: improve comments
157a943 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: consolidate and update FPGA config examples
24a28a5 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga/ip/i2c: remove dead code and improve comment.
6a8b138 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling @stv0g
fpga: Apply suggestions from code review
c44d3c6 
Co-authored-by: Steffen Vogel <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: improve code style
8ce4824 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: remove exceptions from AxisCache
ae5efeb 
Signed-off-by: Niklas Eiling <[email protected]>
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