Skip to content
View zeddo258's full-sized avatar

Block or report zeddo258

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Python Python Public

  2. cycu cycu Public

    CSS

  3. Software_Borrower Software_Borrower Public

  4. ALU-Design ALU-Design Public

    Verilog

  5. DS2EX4 DS2EX4 Public

    C++

  6. 5-Stage-Pipeline-CPU 5-Stage-Pipeline-CPU Public

    Forked from Yingyu18/5-Stage-Pipeline-CPU

    使用Verilog HDL與Modelsim模擬器,以ALU Design 為基礎,設計一個Pipelined MIPS-Lite CPU,內含16道指令(add, sub, and, or, sll, slt, lw, sw, beq, bne, j, multu, mfhi, mflo, nop)。

    Verilog