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5-Stage-Pipeline-CPU
5-Stage-Pipeline-CPU PublicForked from Yingyu18/5-Stage-Pipeline-CPU
使用Verilog HDL與Modelsim模擬器,以ALU Design 為基礎,設計一個Pipelined MIPS-Lite CPU,內含16道指令(add, sub, and, or, sll, slt, lw, sw, beq, bne, j, multu, mfhi, mflo, nop)。
Verilog
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