merge enhancement/csrfiles into develop

Signed-off-by: Ruige <[email protected]>
whutddk · Apr 29, 2023 · ff7b534 · ff7b534
1 parent 58ab13a
commit ff7b534
Show file tree

Hide file tree

Showing 23 changed files with 670 additions and 1,879 deletions.
diff --git a/.github/workflows/BuildAndTest.yml b/.github/workflows/BuildAndTest.yml
@@ -53,7 +53,7 @@ jobs:
 
           cp ${GITHUB_WORKSPACE}/LICENSE.Apache ${GITHUB_WORKSPACE}/../
           cp ${GITHUB_WORKSPACE}/LICENSE.NPL ${GITHUB_WORKSPACE}/../
-          cp -R target/scala-2.12/api ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
+          cp -R target/scala-2.13/api ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
 
           cd ${GITHUB_WORKSPACE}/generated/Release/
           tar -cvf Rift2300-Release.tar Rift2300/*

diff --git a/Makefile b/Makefile
@@ -244,7 +244,7 @@ fpuisa += rv64uf-v-move
 fpuisa += rv64uf-p-recoding
 fpuisa += rv64uf-v-recoding
 
-isa ?= $(aluisa) $(bruisa) $(lsuisa) $(privisa) $(mulisa) # $(fpuisa) 
+isa ?= $(aluisa) $(bruisa) $(lsuisa) $(privisa) $(mulisa)# $(fpuisa) 
 # isa ?= $(fpuisa)
 
 

diff --git a/build.sbt b/build.sbt
@@ -4,7 +4,7 @@
 
 ThisBuild / scalaVersion     := "2.13.10"
 
-ThisBuild / version          := "2.3.5"//-SNAPSHOT
+ThisBuild / version          := "2.3.6"//-SNAPSHOT
 ThisBuild / organization     := "io.github.whutddk"
 val chiselVersion = "3.5.6"
 

diff --git a/src/main/scala/Config.scala b/src/main/scala/Config.scala
@@ -441,23 +441,6 @@ class Rift2360 extends Config((_, _, _) => {
 class Rift2370 extends Config((_, _, _) => {
   case RiftParamsKey => RiftSetting(
     hasVector = false,
-
-    aluNum = 1,
-
-    dptEntry = 4,
-
-    icacheParameters = IcacheParameters(
-      bk = 1,
-      cb = 2,
-      cl = 128
-    ),
-    dcacheParameters = DcacheParameters(
-      bk = 2,
-      cb = 2,
-      cl = 128,
-      stEntry = 4,
-      sbEntry = 4,
-    ),
   )
 })
 

diff --git a/src/main/scala/Parameters.scala b/src/main/scala/Parameters.scala
@@ -180,7 +180,7 @@ case class RiftSetting(
   xRegNum: Int = 64,
   fRegNum: Int = 64,
   vRegNum: Int = 64,
-  cRegNum: Int = 8,
+  // cRegNum: Int = 8,
 
   pmpNum: Int = 1,
   hpmNum: Int = 4,
@@ -275,7 +275,7 @@ trait HasRiftParameters {
   def vRegNum = riftSetting.vRegNum
   def maxRegNum = xRegNum max fRegNum max vRegNum
 
-  def cRegNum = riftSetting.cRegNum
+  // def cRegNum = riftSetting.cRegNum
 
   def pmpNum = riftSetting.pmpNum
   def hpmNum = riftSetting.hpmNum

diff --git a/src/main/scala/rift2Chip/Rift2Chip.scala b/src/main/scala/rift2Chip/Rift2Chip.scala
@@ -72,7 +72,7 @@ class Rift2Chip(isFlatten: Boolean = false)(implicit p: Parameters) extends Lazy
   val nDevices = 31
   val i_plic = LazyModule( new Plic( nHarts = 1, nPriorities = 8, nDevices = nDevices ))
   val sifiveCache = LazyModule(new InclusiveCache(
-      cache = CacheParameters( level = 2, ways = 2, sets = 64, blockBytes = l1DW/8, beatBytes = l1BeatBits/8, hintsSkipProbe = false ),
+      cache = CacheParameters( level = 2, ways = 8, sets = 2048, blockBytes = l1DW/8, beatBytes = l1BeatBits/8, hintsSkipProbe = false ),
       micro = InclusiveCacheMicroParameters( writeBytes = memBeatBits/8, memCycles = 40, portFactor = 4),
       control = None
     ))