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continue in THUMB mode if CPSR register has T bit #1801

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continue in THUMB mode if CPSR register has T bit #1801

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d4ac645
continue in THUMB mode if CPSR register has T bit
lowlyw Mar 9, 2023
7090776
Update uc.c
lowlyw Mar 9, 2023
43ac502
Update uc.c
lowlyw Mar 9, 2023
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12 changes: 10 additions & 2 deletions uc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -788,9 +788,17 @@ uc_err uc_emu_start(uc_engine *uc, uint64_t begin, uint64_t until,
break;
#endif
#ifdef UNICORN_HAS_ARM
case UC_ARCH_ARM:
case UC_ARCH_ARM: {
// HACK: force bit 0 of pc to 1 if in thumb mode when starting.
// Thumb mode is determined by bit 5 of the CPSR register.
uint32_t cpsr;
uc_reg_read(uc, UC_ARM_REG_CPSR, &cpsr);
if (cpsr & 0x20) {
begin_pc32 |= 1;
}
uc_reg_write(uc, UC_ARM_REG_R15, &begin_pc32);
break;
}
#endif
#ifdef UNICORN_HAS_ARM64
case UC_ARCH_ARM64:
Expand Down Expand Up @@ -2431,4 +2439,4 @@ void trace_end(uc_tracer *tracer, trace_loc loc, const char *fmt, ...)
fprintf(stderr, "%.6fus\n",
(double)(end - tracer->starts[loc]) / (double)(1000));
}
#endif
#endif