Scalable-Bilateral-Filtering-on-FPGA

VHDL implimentation of A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering.

Refrences:

[1] K. N. Chaudhury and S. D. Dabhade, “Fast and provably accurate bilateral filtering,” IEEE Transactions on Image Processing, vol. 25, no. 6, pp. 2519-2528, 2016.

[2] S. D. Dabhade, G. N. Rathna and K. N. Chaudhury, “A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering,” IEEE Transactions on Industrial Electronics, vol. 65, no. w, pp. 1459-1469, 2018.