This is experimental code implementing BLAKE2 using the AVX2 instruction set present in the Intel Haswell and later microarchitectures.
It currently implements BLAKE2b, BLAKE2bp, and BLAKE2sp using 3 similar but slightly different approaches: one lets the compiler choose how to permute the message, another one does it manually, and the final one uses the gather instructions introduced with AVX2. Current recorded speeds for long messages are:
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3.19 cycles per byte on Haswell for BLAKE2b;
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1.37 cycles per byte on Haswell for BLAKE2bp;
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1.39 cycles per byte on Haswell for BLAKE2sp.
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3.08 cycles per byte on Skylake for BLAKE2b;
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1.29 cycles per byte on Skylake for BLAKE2bp;
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1.30 cycles per byte on Skylake for BLAKE2sp.