RISCV: Add vector psabi checking.

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move):
	(riscv_vector_psabi_warnning):
	(riscv_arg_has_vector):
	(riscv_pass_in_vector_p):
	(riscv_get_arg_info):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.

Signed-off-by: Yanzhang Wang <[email protected]>
Co-authored-by: Kito Cheng <[email protected]>

gcc/config/riscv/riscv.cc

@@ -2089,8 +2089,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 	}
       return true;
     }
-  /* Expand 
-       (set (reg:QI target) (mem:QI (address))) 
+  /* Expand
+       (set (reg:QI target) (mem:QI (address)))
      to
        (set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
        (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
@@ -2105,7 +2105,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 
       temp_reg = gen_reg_rtx (word_mode);
       zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
-      emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, 
+      emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
 				  zero_extend_p));
       riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
       return true;
@@ -3728,6 +3728,65 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+static void
+riscv_vector_psabi_warnning ()
+{
+  warning (OPT_Wpsabi, "ABI for the vector type is currently in experimental"
+       "stage and may changes in the upcoming version of GCC.");
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    if (!TYPE_P (TREE_TYPE (f)))
+	      break;
+
+	    if (VECTOR_TYPE_P (type))
+	      is_vector = true;
+	    else
+	      is_vector = riscv_arg_has_vector (TREE_TYPE (f));
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = true;
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      riscv_vector_psabi_warnning ();
+      warned = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3812,6 +3871,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
 	}
     }
 
+  /* Only check existing of vector type.  */
+  riscv_pass_in_vector_p (type);
+
   /* Work out the size of the argument.  */
   num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
   num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

gcc/testsuite/gcc.target/riscv/vector-abi-1.c

@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}

gcc/testsuite/gcc.target/riscv/vector-abi-2.c

@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}