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add Cortex-A72 Spectre v4 (CVE-2018-3639) mitigation #115

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11 changes: 10 additions & 1 deletion armstubs/Makefile
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
BINS=armstub.bin armstub7.bin armstub8-32.bin armstub8-32-gic.bin armstub8.bin armstub8-gic.bin armstub8-gic-highperi.bin
BINS=armstub.bin armstub7.bin armstub8-32.bin armstub8-32-gic.bin armstub8.bin armstub8-gic.bin armstub8-gic-highperi.bin armstub8-gic-spectrev4.bin

CC8?=aarch64-linux-gnu-gcc
LD8?=aarch64-linux-gnu-ld
Expand Down Expand Up @@ -26,6 +26,9 @@ clean :
%8-gic-highperi.o: %8.S
$(CC8) -DGIC=1 -DHIGH_PERI=1 -DBCM2711=1 -c $< -o $@

%8-gic-spectrev4.o: %8.S
$(CC8) -DGIC=1 -DSPECTRE_V4=1 -DBCM2711=1 -c $< -o $@

%8-32.o: %7.S
$(CC7) -DBCM2710=1 -c $< -o $@

Expand All @@ -41,6 +44,9 @@ clean :
%8-gic-highperi.elf: %8-gic-highperi.o
$(LD8) --section-start=.text=0 $< -o $@

%8-gic-spectrev4.elf: %8-gic-spectrev4.o
$(LD8) --section-start=.text=0 $< -o $@

%8.elf: %8.o
$(LD8) --section-start=.text=0 $< -o $@

Expand All @@ -53,6 +59,9 @@ clean :
%8-gic-highperi.tmp: %8-gic-highperi.elf
$(OBJCOPY8) $< -O binary $@

%8-gic-spectrev4.tmp: %8-gic-spectrev4.elf
$(OBJCOPY8) $< -O binary $@

%8.tmp: %8.elf
$(OBJCOPY8) $< -O binary $@

Expand Down
9 changes: 9 additions & 0 deletions armstubs/armstub8.S
Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,9 @@
#define ACTLR_VAL \
(BIT(0) | BIT(1) | BIT(4) | BIT(5) | BIT(6))

#define CPUACTLR_EL1 S3_1_C15_C2_0
#define CPUACTLR_EL1_DLPS BIT(55)

#define CPUECTLR_EL1 S3_1_C15_C2_1
#define CPUECTLR_EL1_SMPEN BIT(6)

Expand Down Expand Up @@ -130,6 +133,12 @@ _start:
mov x0, #CPUECTLR_EL1_SMPEN
msr CPUECTLR_EL1, x0

#ifdef SPECTRE_V4
/* mitigate Spectre v4 */
mov x0, #CPUACTLR_EL1_DLPS
msr CPUACTLR_EL1, x0
#endif

#ifdef GIC
bl setup_gic
#endif
Expand Down