samples: support for nrf54l15 with tfm

[KRKNWK-19489] Fix faults after application start. Align mfg address with non tfm variant. Disable logs in tf-m, pins are needed for Semtech. Signed-off-by: Krzysztof Taborowski <[email protected]>
nrfconnect · Nov 7, 2024 · 87deede · 87deede
1 parent 5ea2aee
commit 87deede
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Showing 4 changed files with 172 additions and 141 deletions.
diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp_ns.conf b/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp_ns.conf
@@ -7,8 +7,15 @@
 # Multirole is the only currently supported role by SoftDevice.
 CONFIG_BT_LL_SOFTDEVICE_MULTIROLE=y
 
+# nRF54L15 requires bigger stack sizes than nRF52/nRF53 families
+CONFIG_MPSL_WORK_STACK_SIZE=2048
+
 # Not supported for 54L15 _NS
 CONFIG_FPROTECT=n
 
 # Set the ZMS sector count to match the settings partition size that is 40 kB for this application.
 CONFIG_SETTINGS_ZMS_SECTOR_COUNT=10
+
+# Disable tf-m uart to reuse pins for semtech
+CONFIG_TFM_LOG_LEVEL_SILENCE=y
+CONFIG_TFM_SECURE_UART=n
diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp_ns.overlay b/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp_ns.overlay
@@ -4,36 +4,7 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-&pinctrl {
-	spi21_default: spi21_default {
-		group1 {
-			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
-				<NRF_PSEL(SPIM_MISO, 1, 11)>,
-				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
-		};
-	};
-
-	spi21_sleep: spi21_sleep {
-		group1 {
-			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
-				<NRF_PSEL(SPIM_MISO, 1, 11)>,
-				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
-			low-power-enable;
-		};
-	};
-};
-
- sid_semtech: &spi21 {
-	compatible = "nordic,nrf-spim";
-	status = "okay";
-	cs-gpios = <&gpio2 0xa GPIO_PULL_UP>;
-	pinctrl-0 = <&spi21_default>;
-	pinctrl-1 = <&spi21_sleep>;
-	pinctrl-names = "default", "sleep";
-	clock-frequency = <DT_FREQ_M(8)>;
-};
-
-/{
+ /{
 	aliases {
 		state-notifier-connected = &led0;
 		state-notifier-time-sync = &led1;
@@ -44,25 +15,34 @@
 	semtech_sx1262_gpios{
 		compatible = "gpio-keys";
 		semtech_sx1262_reset_gpios: reset {
-			gpios = <&gpio0 0x2 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
+			gpios = <&gpio2 8  (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
 			label = "semtech_sx1262 Reset";
 		};
 		semtech_sx1262_busy_gpios: busy {
-			gpios = <&gpio0 0x0 0x0>;
+			gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH)>;
 			label = "semtech_sx1262 Busy";
 		};
 		semtech_sx1262_antenna_enable_gpios: antena_enable {
-			gpios = <&gpio0 0x1 0x0>;
+			gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH)>;
 			label = "semtech_sx1262 Antena Enable";
 		};
 		semtech_sx1262_dio1_gpios: dio1 {
-			gpios = <&gpio0 0x3  0x0>;
+			gpios = <&gpio1 11  (GPIO_ACTIVE_HIGH|GPIO_PULL_DOWN)>;
 			label = "semtech_sx1262 DIO1";
 		};
-	};	
+	};
+};
+
+sid_semtech: &spi30 {
+	compatible = "nordic,nrf-spim";
+	status = "okay";
+	cs-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi30_default_alt>;
+	pinctrl-1 = <&spi30_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	clock-frequency = <DT_FREQ_M(8)>;
 };
 
-// restore full RRAM and SRAM space - by default some parts are dedicated to FLRP
 &cpuapp_rram {
 	reg = <0x0 DT_SIZE_K(1524)>;
 };
@@ -72,6 +52,49 @@
 	ranges = <0x0 0x20000000  0x40000>;
 };
 
+&pinctrl {
+	spi30_default_alt: spi30_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
+				<NRF_PSEL(SPIM_MISO, 0, 2)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 1)>;
+		};
+	};
+
+	spi30_sleep_alt: spi30_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
+				<NRF_PSEL(SPIM_MISO, 0, 2)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 1)>;
+			low-power-enable;
+		};
+	};
+};
+
+&adc {
+	status = "disabled";
+};
+&uart21 {
+	status = "disabled";
+};
+&pwm20 {
+	status = "disabled";
+};
+&i2c20 {
+	status = "disabled";
+};
+&spi20 {
+	status = "disabled";
+};
+&spi22 {
+	status = "disabled";
+};
+
+// TODO: re-enable HWFC once it's fixed
+&uart20 {
+	/delete-property/ hw-flow-control;
+};
+
 
 // Change IRQ ids to handle button interrupts.