Firtool 1.56.0 Release

What's Changed

• [Pipeline] Add non-stallable pipeline stages by @mortbopet in #6018
• [OM] Handle AnyType casts in Evaluator. by @mikeurbach in #6106
• [OM][firtool] Add FreezePaths pass by @youngar in #6069
• [CI] Use macOS universal wheels for M-series, add Python 3.9 and 3.11 support by @leonardt in #5822
• Add OMInstanceTarget path kind by @youngar in #6123
• [Arc] Introduce vectorize operation by @maerhart in #6120
• [Pipeline] Fix issue in ExplicitRegs by @mortbopet in #6118
• [Ibis] Add ibis reblock pass by @mortbopet in #6089
• [HW] Support parametric UnpackedArrayType in hw-specialize by @mortbopet in #6119
• [Ibis] Rename ibis.block -> ibis.sblock by @mortbopet in #6125
• [FIRRTL][IMCP] Fix handling of refsub, send/resolve, fields. by @dtzSiFive in #6100
• [FIRRTL][Parser] Wires of non-agg non-hw should have droppable names. by @dtzSiFive in #6102
• [FIRRTL][Inliner] Use wires for all. by @dtzSiFive in #6127
• [FIRRTL][LowerClasses] Handle InstanceTarget. by @dtzSiFive in #6126
• [PyCDE] Move off of msft.module to hw.module by @teqdruid in #6122
• [OM] Add path append op by @prithayan in #6073
• [HW] Unify port location arrays and port attribute arrays by @darthscsi in #6116
• [FIRRTL][Dedup] An extmodule without defname is unique. by @dtzSiFive in #6129
• [FIRRTL][Dedup] Skip modules with syms we can't drop, classes. by @dtzSiFive in #6133
• [Arc] Include pass base only where needed by @maerhart in #6140
• [Arc] Improve performance of state update legalization by @fabianschuiki in #6137
• [Arc] Add LowerVectorizations pass by @maerhart in #6141
• [Arc] Allow top-level logic in LowerState; detect clock edges by @fabianschuiki in #6142
• [Handshake] Allow handshake ops to be used outside of a handshake.func by @mortbopet in #6132
• [Seq] Convert seq.clock_gate to use the clock type exclusively by @nandor in #6134
• [Seq] Switch all seq ops to use seq.clock by @nandor in #6139
• [Seq] Lower clock types nested within aggregates by @nandor in #6138
• [FIRRTL][FIRParser] Add AnyRef cast as-needed for agg prop expr's. by @dtzSiFive in #6135
• [scf-to-calyx]Support for function call by @linuxlonelyeagle in #5965
• [Firtool] Move the remaining pass additions into lib by @SpriteOvO in #6094
• [Ibis] Add ibis.sblock inlining operations and passes by @mortbopet in #6145
• [HW][Python] Add name getters for ModuleType by @uenoku in #6149
• [OM] Python bindings for om integer by @prithayan in #6042
• [Ibis] Allow multiple return values for ibis.method by @mortbopet in #6151
• [NFC][Handshake] Adjust handshake interface defs and file locs by @mortbopet in #6150
• [ExportVerilog] Support CallSiteLoc and NameLoc emission by @mortbopet in #6131
• [ExportVerilog] Add verilog debug locations to output MLIR by @prithayan in #6092
• [FIRRTL][IMDCE] Mark all objects as alive by @rwy7 in #6157
• [ExportVerilog] Remove useless assert from NameCollector by @fabianschuiki in #6147
• [CI] Hotfix macosx python wheel by @leonardt in #6158
• [MSFT] Make AppID discovery an index rather than a pass by @teqdruid in #6152
• [PyCDE] Switch over to new AppIDIndex by @teqdruid in #6160
• [HW] Align instance_like_impl verification with getReferencedModule by @mortbopet in #6155
• [NFC][ExportVerilog] Move location emission functions to class by @mortbopet in #6154
• [CFToHandshake] Refactor towards genericness by @mortbopet in #6156
• [Ibis] Add ibis.method.df operation by @mortbopet in #6163
• [HW] Fix ModuleType::getInputType to return InOutType for InOut port by @uenoku in #6162

New Contributors

• @leonardt made their first contribution in #5822

Full Changelog: firtool-1.55.0...firtool-1.56.0