Firtool Release 1.40.0

What's Changed

• [ESI][Data windows] Introduce wrap/unwrap by @teqdruid in #4953
• [HW] Size enums to the number of tags by @darthscsi in #4988
• [FIRRTL] Add MemOp prefix attr, remove groupID attr by @fabianschuiki in #4952
• [Arc] Memory ops: optional enables and folders by @maerhart in #4976
• [Arc] Add StateOp folder by @maerhart in #4979
• [FIRRTL] lower plusargs to initial block by @darthscsi in #4999
• [FIRRTL] Parse {force,release}{,_initial}. by @dtzSiFive in #4990
• [Seq] Add enums for RUW/WUW behavior of memories by @fabianschuiki in #5007
• [FIRRTL] Add getFieldNameAttr helper to SubTagOp by @youngar in #5016
• [HW] Add type inference to UnionExtractOp by @youngar in #5015
• [FIRRTL] Lower complex enums to use hw enums for the tag by @youngar in #5019
• [ExportVerilog] Handle printing of union types by @youngar in #5020
• [ExportVerilog] Union type output support by @teqdruid in #5001
• [InferWidths] Add support for inferring through ref.sub. by @dtzSiFive in #5000
• [FIRRTL][InferResets] Infer through ref.sub. by @dtzSiFive in #4998
• [PyCDE] [Docs] Mention to add upstream remote to fetch tags when building wheels by @VMois in #5027
• [Handshake] Remove cmerge return type inference by @RamirezLucas in #5021
• [Arc] StripSV: fix dialect dependencies, option and warning for replacing external module instances by @maerhart in #5028
• [ExportVerilog] Handle printing of UnionExtractOp by @youngar in #5022
• [HW] implement missing EnumConstantOp builder by @youngar in #5030
• [HW] Add an enum comparison operation by @youngar in #5032
• Bump LLVM by @youngar in #5029
• [FIRRTL][Dedup] Print integer constants as hexadecimal by @youngar in #5033
• [Docs] Include Arc and SystemC in Passes.md by @maerhart in #5036
• [ExportVerilog] Add support for EnumCmpOp by @youngar in #5035
• [FIRRTL] Add MatchOp statement by @youngar in #5037
• [FIRRTL] Add IsTagOp to test enumeration variant by @youngar in #5038
• [FIRRTL] Add LowerMatches pass by @youngar in #5039
• [Seq] Add an option to lower seq.compreg to always blocks by @nandor in #5040
• [FIRRTL][LowerToHW] Handle SubTag and IsTag operations by @youngar in #5041
• [FIRRTL] Support EnumTypes in walkGroundTypes(Type) utility by @youngar in #5042
• [Arc] Infer StateOp reset from CompReg by @TaoBi22 in #4997
• [Arc] Remove erroneous reset nesting in LowerState pass by @TaoBi22 in #5023
• [FIRRTLFolds] Fix crashes in bundle/vector create folders. by @dtzSiFive in #5048
• [FIRRTL] Alternative Connect/Invalidate Parsing by @seldridge in #5049
• [LowerTypes][NFC] Minor touchups. by @dtzSiFive in #5050
• Enable --view-op-graph for circt-opt by @mortbopet in #5046
• [ESI][Windows] Lower Window ports to unions by @teqdruid in #5026
• [Handshake] Remove handshake.select by @mortbopet in #5045
• Bump LLVM by @chick in #5054
• [LoopSchedule] Move PipelineWhile and related ops from Pipeline to LoopSchedule by @andrewb1999 in #4947
• [NFC][Support] Factor out TypeConversionPattern into support lib by @teqdruid in #5055
• [NFC][ESI] Refactor ESI passes into individual files by @teqdruid in #5058
• [ESI][MSFT] Fix all clang-tidy-10 warnings by @teqdruid in #5059
• [FIRRTL] Parse 3.0.0 connect and invalidate by @seldridge in #5057
• [PyCDE] Expose ESI list type by @teqdruid in #5060
• [ESI] Fix capnp relative include paths after refactor. by @dtzSiFive in #5061
• [FIRRTL] Uninferred Width Cast by @darthscsi in #5047
• [ETC] Don't relocate instances that were only in extracted test code. by @mikeurbach in #5064
• [Arc][LowerState] Fix combinational loop false positives by @fabianschuiki in #5068
• [FIRRTL] Add clock gate intrinsic by @fabianschuiki in #5073
• LLVM Bump by @nandor in #5070
• [FIRRTL] FoldReadWritePorts: Fix heap-use-after-free. by @dtzSiFive in #5078
• [FIRRTL][InferWidths] Support enum types by @youngar in #5079
• [ExportVerilog] Add support for UnionCreate op. by @youngar in #5081
• [FIRRTL] firtool: Run merge-cnxns regardless of agg preserv. by @dtzSiFive in #5086
• [OM] Add a Reference type. by @mikeurbach in #5083
• [OM] Add Reference attribute. by @mikeurbach in #5084
• [FIRRTL] RefType: Implement FieldIDTypeInterface. by @dtzSiFive in #5087
• [Seq] Add clock gate operation by @fabianschuiki in #5082
• [FIRRTL][LowerToHW] Support FEnumCreateOp by @youngar in #5080
• [ExportVerilog] Remove uneeded parenthesis around UnionCreate by @youngar in #5091
• [FIRRTL][ExpandWhens] Use port locs when emitting init errors by @youngar in #5092
• [FIRRTL] Remove some unused datastructures by @youngar in #5093
• [FIRRTL] Support multiple ports for smem by @SpriteOvO in #4850
• [LowerToHW] Gate force/release on ifndef SYNTHESIS, not VERILATOR. by @dtzSiFive in #5090

New Contributors

• @VMois made their first contribution in #5027
• @chick made their first contribution in #5054

Full Changelog: firtool-1.39.0...firtool-1.40.0