Repository documenting the Summer Internship’24 on Digital System Prototyping using FPGAs (NIELIT Calicut)
Our key focus is on the System specification ,Architectural design ,Functional design and logic design ,and finaly the circuit design
The Gajski-Kuhn Y-chart is a model, which captures the considerations in designing semiconductor devices.
The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the domains can be divided into levels of abstraction, using concentric rings.
At the top level (outer ring), we consider the architecture of the chip; at the lower levels (inner rings), we successively refine the design into finer detailed implementation −
Creating a structural description from a behavioral one is achieved through the processes of high-level synthesis or logical synthesis.
Creating a physical description from a structural one is achieved through layout synthesis.
The RTL files and the testbench files are text files that need to be analyzed before you can even think about simulation. A tool called a parser will read every HDL file and check that the syntax is correct. Every language has a LRM, a (language reference manual) that defines the syntax that is valid. Several HDL languages have different versions, hence different LRM requirements. The compiler is in fact a parser that checks every HDL file for syntax errors. It will report warnings and errors related to the code you have written. All files, RTL and behavoural need to be syntactically correct before you can go to the next step, elaboration.
Synthesis is the process of converting RTL code, typically written in hardware description languages like Verilog or VHDL, into a gate-level netlist. It involves mapping the functionality specified in the RTL code to a library of standard cells, such as NAND, NOR, XOR gates, etc., provided by the target technology.
Things that we need for the synthesis..... RTL Code,Technology Libraries,Constraint Files
The need to use GLS (Gate level simulation)
The term "gate level" refers to the netlist view of a circuit, usually produced by logic synthesis. So while RTL simulation is pre-synthesis, GLS is post-synthesis. The netlist view is a complete connection list consisting of gates and IP models with full functional and timing behavior. RTL simulation is a zero delay environment and events generally occur on the active clock edge. GLS can be zero delay also, but is more often used in unit delay or full timing mode. Events may be triggered by the clock, but will propagate according to the delays on each element. The loading and wiring delay models of the netlist can be estimated by the synthesis tools, or can be output from the layout tools. These delay models usually come in the form of an SDF (standard delay format) file.
"Douglas A. Pucknell" - Douglas A. Pucknell
"CMOS Digital IC Circuit analysis and Design"-MC GRAW hill
"Digital integrated circuit design from vlsi architectures to cmos fabrication" - Hubert Kaeslin
In windows go to the following URL link
After installing .exe file Do the following steps
Run the setup and install ModelSim
-
Creating the library in ModelSim.
-
Name the library as you wish.
-
Creating a new file for the verilog to code the stuff.
-
The window appears where you can enter the code as per the requirement.
writing syntehesizeable code in verilog that actually work
schematic has 6000 pages maximum so we go for
IP means Intelectual Protocols it is the base for REUSABILITY
Bottom-up (bricks n to a building) and top down (reverse) approach ....
Lesser TTM (time to market) is what you will see in the market :) behaviorial codes we do use reg type not net and wire WHY? BLOCKING AND NON BLOCKING STATEMETS IN VERILOG
(changing a value in either one of the inputs causes a EVENT -> leads to another event) hardware is CONCURRENT
Single kernel architecture is better ahm just verilog file no intermidiate files time consumed is vv less :) double kernel arch
you cant tapeout opensource hardware ? damn ..... primetime and caliber
get the tool list of the companies and compile them :)
with a single cond statement y = sel ? a:b;
8x8 64 bit memory reg [0:63] mem [0:7][0:7] how to acess and find the very first bit of the very last 7 of 7 th place in the mem register
difference between $ display nd $ monitor display is only for 1 event monitor is used for every single EVENT :)