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papi_events.csv: Add preset events support for FUJITSU-MONAKA
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This commit adds preset events support for FUJITSU-MONAKA.
Also update arm_cpu_util.c to show the processor name in papi_hardware_avail command.
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@Akio-Kakuno @Yoshihiro-Furudera
Akio-Kakuno authored and Yoshihiro-Furudera committed Nov 14, 2024
1 parent 366ac71 commit 894f2ed
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4 changes: 4 additions & 0 deletions src/components/sysdetect/arm_cpu_utils.c
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
#define NAMEID_BROADCOM_THUNDERX2 0x516
#define NAMEID_CAVIUM_THUNDERX2 0x0af
#define NAMEID_FUJITSU_A64FX 0x001
#define NAMEID_FUJITSU_MONAKA 0x003
#define NAMEID_HISILICON_KUNPENG 0xd01
#define NAMEID_APM_XGENE 0x000
#define NAMEID_QUALCOMM_KRAIT 0x040
Expand Down Expand Up @@ -334,6 +335,9 @@ name_id_fujitsu_cpu_get_name( int name_id, char *name )
case NAMEID_FUJITSU_A64FX:
strcpy(name, "Fujitsu A64FX");
break;
case NAMEID_FUJITSU_MONAKA:
strcpy(name, "Fujitsu FUJITSU-MONAKA");
break;
default:
papi_errno = PAPI_ENOSUPP;
}
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79 changes: 79 additions & 0 deletions src/papi_events.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -2435,6 +2435,85 @@ PRESET,PAPI_TLB_TL,DERIVED_ADD,L1D_TLB_REFILL,L2D_TLB_REFILL
#NOT_IMPLEMENTED,PAPI_CSR_TOT,Total store conditional instructions
#NOT_IMPLEMENTED,PAPI_PRF_DM,Data prefetch cache misses

##############################
# ARM Fujitsu FUJITSU-MONAKA #
##############################
CPU,arm_monaka
#
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L3_DCM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L3_TCM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_DM_RD
PRESET,PAPI_L3_STM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_DM_WR
PRESET,PAPI_BRU_IDL,NOT_DERIVED,BR_COMP_WAIT
PRESET,PAPI_FXU_IDL,DERIVED_SUB,EU_COMP_WAIT,FL_COMP_WAIT
PRESET,PAPI_FPU_IDL,NOT_DERIVED,FL_COMP_WAIT
PRESET,PAPI_LSU_IDL,NOT_DERIVED,LD_COMP_WAIT
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L2I_TLB_REFILL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L2D_TLB_REFILL,L2I_TLB_REFILL
PRESET,PAPI_L1_LDM,DERIVED_ADD,L1D_CACHE_REFILL_DM_RD,L1I_CACHE_REFILL_DM_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L1D_CACHE_REFILL_DM_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_DM_RD
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_CACHE_REFILL_DM_WR
PRESET,PAPI_PRF_DM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_PRF
PRESET,PAPI_L3_DCH,NOT_DERIVED,L2D_CACHE_REFILL_L3D_HIT
PRESET,PAPI_MEM_SCY,DERIVED_ADD,STALL_FRONTEND_MEMBOUND,STALL_BACKEND_MEMBOUND
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_STL_CCY,NOT_DERIVED,_0INST_COMMIT
PRESET,PAPI_FUL_CCY,DERIVED_POSTFIX,N0|N1|-|N2|-|N3|-|N4|-|N5|-|,CPU_CYCLES,_0INST_COMMIT,_1INST_COMMIT,_2INST_COMMIT,_3INST_COMMIT,_4INST_COMMIT
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_FMA_INS,NOT_DERIVED,FP_FMA_SPEC
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_INT_INS,NOT_DERIVED,INT_SPEC
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_SPEC
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_LST_INS,NOT_DERIVED,LDST_SPEC
PRESET,PAPI_SYC_INS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|,ISB_SPEC,DSB_SPEC,DMB_SPEC,CSDB_SPEC
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
PRESET,PAPI_L2_DCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_DCA,NOT_DERIVED,L2D_CACHE_REFILL_L3D_CACHE
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_DCR,NOT_DERIVED,L3D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_DCW,DERIVED_SUB,L2D_CACHE_REFILL_L3D_CACHE,L3D_CACHE_RD
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L3_TCH,NOT_DERIVED,L2D_CACHE_REFILL_L3D_HIT
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_TCA,NOT_DERIVED,L2D_CACHE_REFILL_L3D_CACHE
PRESET,PAPI_L2_TCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_TCR,NOT_DERIVED,L3D_CACHE_RD
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_TCW,DERIVED_SUB,L2D_CACHE_REFILL_L3D_CACHE,L3D_CACHE_RD
PRESET,PAPI_FML_INS,NOT_DERIVED,FP_MUL_SPEC
PRESET,PAPI_FDV_INS,NOT_DERIVED,FP_DIV_SPEC
PRESET,PAPI_FSQ_INS,NOT_DERIVED,FP_SQRT_SPEC
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SP_SCALE_OPS_SPEC,FP_SP_FIXED_OPS_SPEC
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_DP_SCALE_OPS_SPEC,FP_DP_FIXED_OPS_SPEC
PRESET,PAPI_VEC_SP,NOT_DERIVED,ASE_SVE_FP_SP_SPEC
PRESET,PAPI_VEC_DP,NOT_DERIVED,ASE_SVE_FP_DP_SPEC
PRESET,PAPI_REF_CYC,NOT_DERIVED,CNT_CYCLES

#
CPU,mips_74k
#
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