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WIP: Experimental support for DSP (Do not merge) #3284

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6 changes: 4 additions & 2 deletions utils/update_arch_timings.py
Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,7 @@ def find_timings(timings, bel, location, site, bels, corner, speed_type):

def get_timing(cell, delay, corner, speed_type):
"""
Gets timing for a particular cornet case. If not fount then chooses
Gets timing for a particular corner case. If not found then chooses
the next best one.
"""
entries = cell[delay]['delay_paths'][corner.lower()]
Expand Down Expand Up @@ -189,7 +189,9 @@ def get_bel_timings(element, timings, bels, corner, speed_type):
bel = pb_chain[-1]
location = pb_chain[-2]
site = remove_site_number(pb_chain[1])




result = find_timings(
timings, bel, location, site, bels, corner, speed_type
)
Expand Down
37 changes: 20 additions & 17 deletions xilinx/common/primitives/dsp48e1/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -1,17 +1,20 @@
add_subdirectory(nreg)
add_subdirectory(alu)
add_subdirectory(alumode_mux)
add_subdirectory(carryinsel_logic)
add_subdirectory(carryinsel_mux)
add_subdirectory(creg_mux)
add_subdirectory(dual_ad_preadder)
add_subdirectory(dual_b_reg)
add_subdirectory(inmode_mux)
add_subdirectory(mult25x18)
add_subdirectory(mult_mux)
add_subdirectory(opmode_mux)
add_subdirectory(xmux)
add_subdirectory(ymux)
add_subdirectory(zmux)
add_file_target(FILE dsp48e1.sim.v SCANNER_TYPE verilog)
v2x(NAME dsp48e1 SRCS dsp48e1.sim.v)
#add_subdirectory(nreg)
#add_subdirectory(alu)
#add_subdirectory(alumode_mux)
#add_subdirectory(carryinsel_logic)
#add_subdirectory(carryinsel_mux)
#add_subdirectory(creg_mux)
#add_subdirectory(dual_ad_preadder)
#add_subdirectory(dual_b_reg)
#add_subdirectory(inmode_mux)
#add_subdirectory(mult25x18)
#add_subdirectory(mult_mux)
#add_subdirectory(opmode_mux)
#add_subdirectory(xmux)
#add_subdirectory(ymux)
#add_subdirectory(zmux)
#add_file_target(FILE dsp48e1.sim.v SCANNER_TYPE verilog)
#v2x(NAME dsp48e1 SRCS dsp48e1.sim.v)

add_file_target(FILE dsp48e1.model.xml SCANNER_TYPE xml)
add_file_target(FILE dsp48e1.pb_type.xml SCANNER_TYPE xml)
57 changes: 57 additions & 0 deletions xilinx/common/primitives/dsp48e1/dsp48e1.model.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
<models>
<model name="DSP48E1_VPR">
<input_ports>
<port clock="CLK" name="A" combinational_sink_ports="ACOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="B" combinational_sink_ports="BCOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="C" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="D" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="OPMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="ALUMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="CARRYIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="CARRYINSEL" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="INMODE" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="CEA1"/>
<port clock="CLK" name="CEA2"/>
<port clock="CLK" name="CEB1"/>
<port clock="CLK" name="CEB2"/>
<port clock="CLK" name="CEC"/>
<port clock="CLK" name="CED"/>
<port clock="CLK" name="CEM"/>
<port clock="CLK" name="CEP"/>
<port clock="CLK" name="CEAD"/>
<port clock="CLK" name="CEALUMODE"/>
<port clock="CLK" name="CECTRL"/>
<port clock="CLK" name="CECARRYIN"/>
<port clock="CLK" name="CEINMODE"/>
<port clock="CLK" name="RSTA"/>
<port clock="CLK" name="RSTB"/>
<port clock="CLK" name="RSTC"/>
<port clock="CLK" name="RSTD"/>
<port clock="CLK" name="RSTM"/>
<port clock="CLK" name="RSTP"/>
<port clock="CLK" name="RSTCTRL"/>
<port clock="CLK" name="RSTALLCARRYIN"/>
<port clock="CLK" name="RSTALUMODE"/>
<port clock="CLK" name="RSTINMODE"/>
<port is_clock="1" name="CLK"/>
<port clock="CLK" name="ACIN" combinational_sink_ports="ACOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="BCIN" combinational_sink_ports="BCOUT CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="PCIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="CARRYCASCIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
<port clock="CLK" name="MULTSIGNIN" combinational_sink_ports="CARRYCASCOUT CARRYOUT MULTSIGNOUT P PATTERNBDETECT PATTERNDETECT PCOUT"/>
</input_ports>
<output_ports>
<port clock="CLK" name="ACOUT"/>
<port clock="CLK" name="BCOUT"/>
<port clock="CLK" name="PCOUT"/>
<port clock="CLK" name="P"/>
<port clock="CLK" name="CARRYOUT"/>
<port clock="CLK" name="CARRYCASCOUT"/>
<port clock="CLK" name="MULTSIGNOUT"/>
<port clock="CLK" name="PATTERNDETECT"/>
<port clock="CLK" name="PATTERNBDETECT"/>
<port clock="CLK" name="OVERFLOW"/>
<port clock="CLK" name="UNDERFLOW"/>
</output_ports>
</model>
</models>
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