CGRA configurable size and instruction update

[benoitdenkinger]

This PR contains two important udpates:

1. The CGRA size can be changed in the heepsilon_cfg.hjson file. The complete platform (HW and SW) is adapted accordingly. The applications however are only compatible with some specific sizes, make sure the platform and your apps are aligned.

2. The direct load and store instructions (LWD and SWD) are no longer automatically incrementing their respective address by 4 for 32-bit accesses. Instead, the immediate field (13 bits) is sign extended and used to increment the address to give more flexibility. For old kernels to be compatible, an immediate value of 4 needs to be added to every LWD and SWD instruction.

[davideschiavone]

once this is merge, please @JuanSapriza update the simulator

[JuanSapriza]

Thank you very much @benoitdenkinger !! This will be a great addition!
Lemme merge the other PR #16 first, then I will try this one.

[JuanSapriza]

@benoitdenkinger could you let @mbelda know when this needs testing? She has the use-case for this

[benoitdenkinger]

@JuanSapriza @mbelda this PR is ready for review. I created a simple test app cgra_check_conf that creates a simple kernel for any CGRA size. I did some test and it seems to work. @mbelda, you can try with your own application and change the CGRA configuration in the heepsilon_cfg.hjson file. I only check the code with verilator for now.

[benoitdenkinger]

Now it is also working with modelsim.

[JuanSapriza]

Hello @benoitdenkinger!
Could you give as quick status-update on this? Should we take over? Is there anything else you were planning to add into it?

[benoitdenkinger]

Hello @JuanSapriza, I tested it with verilator and modelsim changing the CGRA parameters and everything worked fine (it was not extensive tests, but I think there is no major bug). I was not planning to add anything, but the only thing I didn't try is the FPGA implementation.

[mbelda]

I tried my code with a 5x4 CGRA using verilator and it worked fine.

[JuanSapriza]

@mbelda @NicCarp11 would any of you mind testing on the FPGA (i no longer have an FPGA 😢 )

You might need to try something small, like a 3x2 because of resource availability