Renaming all cgra_x_heep reference to heepsilon.

Makefile

@@ -28,7 +28,7 @@ heepsilon-gen:
 	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --pkg-sv hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl
 	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --tpl-sv hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl
 	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/util --tpl-sv hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl
-	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/rtl --pkg-sv hw/rtl/cgra_x_heep_pkg.sv.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/rtl --pkg-sv hw/rtl/heepsilon_pkg.sv.tpl
 	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir sw/external/drivers/cgra --header-c sw/external/drivers/cgra/cgra.h.tpl
 	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/data --pkg-sv hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl
 	bash -c "cd hw/vendor/esl_epfl_cgra/data; source cgra_reg_gen.sh; cd ../../../.."

cgra_x_heep.core → heepsilon.core

@@ -14,8 +14,8 @@ filesets:
     - openhwgroup.org:systems:core-v-mini-mcu
     - eslepfl::cgra
     files:
-    - hw/rtl/cgra_x_heep_pkg.sv
-    - hw/rtl/cgra_x_heep_top.sv
+    - hw/rtl/heepsilon_pkg.sv
+    - hw/rtl/heepsilon_top.sv
     file_type: systemVerilogSource
 
   x_heep_system:
@@ -102,7 +102,7 @@ filesets:
     - hw/fpga/sram_wrapper.sv
     - hw/fpga_cgra/cgra_sram_wrapper.sv
     - hw/fpga_cgra/cgra_clock_gate.sv
-    - hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
+    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv
     file_type: systemVerilogSource
 
   ip-fpga:
@@ -179,7 +179,7 @@ targets:
   default: &default_target
     filesets:
     - files_rtl_generic
-    toplevel: [cgra_x_heep_top]
+    toplevel: [heepsilon_top]
 
   sim:
     <<: *default_target
@@ -277,4 +277,4 @@ targets:
     tools:
       vivado:
         part: xc7z020clg400-1
-    toplevel: [xilinx_cgra_x_heep_wrapper]
+    toplevel: [xilinx_heepsilon_wrapper]

heepsilon_cfg.hjson

@@ -10,10 +10,10 @@
         // This limit can be increased but manual changes are required
         // Maximum number of columns: 32-log2(rcs_num_instr)-log2(max_columns*rcs_num_instr)
         // Default settings enable: 32-log2(32)-log2(4*32) = 20 columns
-        num_columns: 4
+        num_columns: 11
         // Main impact: more rows equals to more context memory banks (i.e., one per row)
         // There should be no limitation compared to the number of rows compared to columns
-        num_rows: 4
+        num_rows: 5
         // It is possible to limit the maximum number of columns a kernel can use (this saves a bit of ressources)
         // The default value should be the same than num_columns, put an number to change it
         max_columns: default

hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv → hw/fpga_cgra/xilinx_heepsilon_wrapper.sv

@@ -2,7 +2,7 @@
 // Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-module xilinx_cgra_x_heep_wrapper
+module xilinx_heepsilon_wrapper
   import obi_pkg::*;
   import reg_pkg::*;
 #(
@@ -89,11 +89,11 @@ module xilinx_cgra_x_heep_wrapper
       .clk_out1_0(clk_gen)
   );
 
-  cgra_x_heep_top #(
+  heepsilon_top #(
         .COREV_PULP (0),
         .FPU        (0),
         .ZFINX (0)
-      ) cgra_x_heep_top_i (
+      ) heepsilon_top_i (
         .clk_i(clk_gen),
         .rst_ni(rst_n),
         .boot_select_i,

hw/rtl/cgra_top.vlt

@@ -4,4 +4,4 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*hw/rtl/cgra_x_heep_top.sv" -match "Signal is not used: 'external_subsystem_powergate_iso'*"
+lint_off -rule UNUSED -file "*hw/rtl/heepsilon_top.sv" -match "Signal is not used: 'external_subsystem_powergate_iso'*"

hw/rtl/cgra_x_heep_pkg.sv.tpl → hw/rtl/heepsilon_pkg.sv.tpl

@@ -2,7 +2,7 @@
 // Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-package cgra_x_heep_pkg;
+package heepsilon_pkg;
 
   import addr_map_rule_pkg::*;
   import core_v_mini_mcu_pkg::*;
@@ -49,4 +49,4 @@ package cgra_x_heep_pkg;
       EXT_SYSTEM_NPERIPHERALS
   ) : 32'd1;
 
-endpackage  // cgra_x_heep_pkg
+endpackage  // heepsilon_pkg

hw/rtl/cgra_x_heep_top.sv → hw/rtl/heepsilon_top.sv

@@ -2,7 +2,7 @@
 // Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-module cgra_x_heep_top #(
+module heepsilon_top #(
     parameter COREV_PULP = 0,
     parameter FPU        = 0,
     parameter ZFINX      = 0,
@@ -49,17 +49,17 @@ module cgra_x_heep_top #(
 
   import obi_pkg::*;
   import reg_pkg::*;
-  import cgra_x_heep_pkg::*;
+  import heepsilon_pkg::*;
 
   // External xbar master/slave and peripheral ports
   obi_req_t ext_xbar_slave_req;
   obi_resp_t ext_xbar_slave_resp;
   reg_req_t ext_periph_slave_req;
   reg_rsp_t ext_periph_slave_resp;
-  obi_req_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_req;
-  obi_req_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_req;
-  obi_resp_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_resp;
-  obi_resp_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_resp;
+  obi_req_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_req;
+  obi_req_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_req;
+  obi_resp_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_resp;
+  obi_resp_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_resp;
   obi_req_t heep_core_instr_req;
   obi_resp_t heep_core_instr_resp;
   obi_req_t heep_core_data_req;
@@ -262,4 +262,4 @@ module cgra_x_heep_top #(
       .external_ram_banks_set_retentive_no(external_ram_banks_set_retentive)
   );
 
-endmodule  // cgra_x_heep_pkg
+endmodule  // heepsilon_pkg

hw/vendor/esl_epfl_cgra/lint/cgra.vlt

@@ -47,14 +47,14 @@ lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signa
 lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'shift_right_result_33b'[32]"
 
 // The tool detect multiple drivers at the same line of code (the tool does not interpret the for loop correctly?)
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
-
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
+
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
 
 // Remove clock gating instance for verilator simulation otherwise sim is failing (verilator v4.2)
 lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/cgra_top.sv" -match "Signal is not used: 'rcs_col_e_s'"

hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md

@@ -8,7 +8,7 @@ For this purpose we support the [CORE-V-XIF](https://docs.openhwgroup.org/projec
 
 Here you can find a list of `X-HEEP` based open-source examples. If you want to include your project in this list, please open an issue with a link to your repository.
 
-* [CGRA-X-HEEP](https://github.com/esl-epfl/cgra_x_heep): A CGRA loosely coupled with X-HEEP.
+* [CGRA-X-HEEP](https://github.com/esl-epfl/heepsilon): A CGRA loosely coupled with X-HEEP.
 * [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x.