this stays in sync

commaai · Nov 15, 2024 · 00b2fdc · 00b2fdc
1 parent 742d961
commit 00b2fdc
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Showing 2 changed files with 10 additions and 8 deletions.
diff --git a/board/stm32h7/peripherals.h b/board/stm32h7/peripherals.h
@@ -135,6 +135,7 @@ void peripherals_init(void) {
   RCC->APB1LENR |= RCC_APB1LENR_TIM7EN;  // DMA trigger timer
   RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;  // tick timer
   RCC->APB1LENR |= RCC_APB1LENR_TIM12EN;  // slow loop
+  RCC->APB1LENR |= RCC_APB1LENR_TIM5EN; // sound trigger timer
 
 #ifdef PANDA_JUNGLE
   RCC->AHB3ENR |= RCC_AHB3ENR_SDMMC1EN; // SDMMC

diff --git a/board/stm32h7/sound.h b/board/stm32h7/sound.h
@@ -44,7 +44,7 @@ void sound_init(void) {
 
   // Init DAC
   register_set(&DAC1->MCR, 0U, 0xFFFFFFFFU);
-  register_set(&DAC1->CR, DAC_CR_TEN1 | (6U << DAC_CR_TSEL1_Pos) | DAC_CR_DMAEN1, 0xFFFFFFFFU);
+  register_set(&DAC1->CR, DAC_CR_TEN1 | (4U << DAC_CR_TSEL1_Pos) | DAC_CR_DMAEN1, 0xFFFFFFFFU);
   register_set_bits(&DAC1->CR, DAC_CR_EN1);
 
   // Setup DMAMUX (DAC_CH1_DMA as input)
@@ -55,13 +55,14 @@ void sound_init(void) {
   register_set(&DMA1_Stream1->FCR, 0U, 0x00000083U);
   DMA1_Stream1->CR = (0b11UL << DMA_SxCR_PL_Pos) | (0b01UL << DMA_SxCR_MSIZE_Pos) | (0b01UL << DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | (1U << DMA_SxCR_DIR_Pos);
 
-  // Init trigger timer (48kHz)
-  register_set(&TIM7->PSC, 0U, 0xFFFFU);
-  register_set(&TIM7->ARR, 2494U, 0xFFFFU);
-  register_set(&TIM7->CR2, (0b10U << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk);
-  register_set(&TIM7->CR1, TIM_CR1_ARPE | TIM_CR1_URS, 0x088EU);
-  TIM7->SR = 0U;
-  TIM7->CR1 |= TIM_CR1_CEN;
+  // Init trigger timer (little slower than 48kHz, pulled in sync by SAI4_FS_B)
+  register_set(&TIM5->PSC, 2600U, 0xFFFFU);
+  register_set(&TIM5->ARR, 100U, 0xFFFFFFFFU); // not important
+  register_set(&TIM5->AF1, (0b0010UL << TIM5_AF1_ETRSEL_Pos), TIM5_AF1_ETRSEL_Msk);
+  register_set(&TIM5->CR2, (0b010U << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk);
+  register_set(&TIM5->SMCR, TIM_SMCR_ECE | (0b00111UL << TIM_SMCR_TS_Pos)| (0b0100UL << TIM_SMCR_SMS_Pos), 0x31FFF7U);
+  TIM5->CNT = 0U; TIM5->SR = 0U;
+  TIM5->CR1 |= TIM_CR1_CEN;
 
   // stereo audio in
   register_set(&SAI4_Block_B->CR1, SAI_xCR1_DMAEN | (0b00UL << SAI_xCR1_SYNCEN_Pos) | (0b100U << SAI_xCR1_DS_Pos) | (0b11U << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU);