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Merge pull request #6404 from chipsalliance/dependabot/submodules/thi…
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…rd_party/tools/circt-verilog-78afda8

build(deps): bump third_party/tools/circt-verilog from `1a592a7` to `78afda8`
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github-actions[bot] authored Nov 12, 2024
2 parents 0029246 + 0edf042 commit 79e5685
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion third_party/tools/circt-verilog
Submodule circt-verilog updated 23 files
+10 −0 include/circt/Dialect/ESI/ESIOps.h
+22 −0 include/circt/Dialect/ESI/ESIStdServices.td
+5 −0 include/circt/Dialect/SMT/SMTOps.td
+2 −1 include/circt/Dialect/SMT/SMTVisitors.h
+23 −3 lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp
+112 −12 lib/Dialect/ESI/ESIOps.cpp
+53 −0 lib/Dialect/ESI/ESIStdServices.cpp
+3 −12 lib/Dialect/ESI/runtime/CMakeLists.txt
+1 −1 lib/Dialect/ESI/runtime/pyproject.toml
+1 −0 lib/Dialect/ESI/runtime/setup.py
+33 −7 lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp
+5 −5 lib/Dialect/FIRRTL/Transforms/InferReadWrite.cpp
+6 −0 lib/Target/ExportSMTLIB/ExportSMTLIB.cpp
+3 −0 test/Conversion/SMTToZ3LLVM/smt-to-z3-llvm.mlir
+2 −1 test/Dialect/ESI/errors.mlir
+24 −1 test/Dialect/ESI/services.mlir
+163 −53 test/Dialect/FIRRTL/emit-metadata.mlir
+2 −2 test/Dialect/FIRRTL/inferRW.mlir
+3 −0 test/Dialect/SMT/basic.mlir
+4 −0 test/Target/ExportSMTLIB/core.mlir
+1 −0 unittests/Dialect/CMakeLists.txt
+9 −0 unittests/Dialect/ESI/CMakeLists.txt
+89 −0 unittests/Dialect/ESI/OpTest.cpp

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