xtensa: fix l32 encode and print

capstone-engine · Nov 3, 2024 · 1f89e09 · 1f89e09
1 parent c143bc1
commit 1f89e09
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Showing 5 changed files with 44 additions and 25 deletions.
diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c
@@ -580,9 +580,7 @@ static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
 	CS_ASSERT(isUIntN(16, Imm) && "Invalid immediate");
-	MCOperand_CreateImm0(
-		Inst,
-		(SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17)));
+	MCOperand_CreateImm0(Inst, OneExtend64(Imm << 2, 18));
 	return MCDisassembler_Success;
 }
 

diff --git a/arch/Xtensa/XtensaInstPrinter.c b/arch/Xtensa/XtensaInstPrinter.c
@@ -148,16 +148,8 @@ static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
 	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_L32RTarget, OpNum);
 	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
 	if (MCOperand_isImm(MC)) {
-		int64_t Value =
-			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
-		int64_t InstrOff = Value & 0x3;
-		Value -= InstrOff;
-		CS_ASSERT(
-			(Value >= -262144 && Value <= -4) &&
-			"Invalid argument, value must be in ranges [-262144,-4]");
-		Value += ((InstrOff + 0x3) & 0x4) - InstrOff;
 		SStream_concat0(O, ". ");
-		printInt64(O, Value);
+		printInt64(O, Xtensa_L32R_Value(MI, OpNum));
 	} else if (MCOperand_isExpr(MC))
 		CS_ASSERT_RET(0 && "unimplemented expr printing");
 	else

diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c
@@ -162,6 +162,20 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
 }
 #endif
 
+int64_t Xtensa_L32R_Value(MCInst *MI, int op_num)
+{
+	int64_t InstrOff = MCOperand_getImm(MCInst_getOperand(MI, (op_num)));
+	CS_ASSERT((InstrOff >= -262144 && InstrOff <= -4) &&
+		  "Invalid argument, value must be in ranges [-262144,-4]");
+	int64_t Value = 0;
+	if (MI->csh->LITBASE & 0x1) {
+		Value = (MI->csh->LITBASE & 0xfffff000) + InstrOff;
+	} else {
+		Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
+	}
+	return Value;
+}
+
 void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num)
 {
 	if (!detail_is_set(MI)) {
@@ -203,20 +217,8 @@ void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num)
 		xop->imm = (int32_t)val;
 	} break;
 	case Xtensa_OP_GROUP_L32RTarget: {
-		int64_t Value =
-			MCOperand_getImm(MCInst_getOperand(MI, (op_num)));
-		int32_t InstrOff = (uint32_t)OneExtend32(Value, 16) << 2;
-		CS_ASSERT(
-			(InstrOff >= -262144 && InstrOff <= -4) &&
-			"Invalid argument, value must be in ranges [-262144,-4]");
-		if (MI->csh->LITBASE & 0x1) {
-			Value = ((MI->csh->LITBASE & 0xfffff000) >> 12) +
-				InstrOff;
-		} else {
-			Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
-		}
 		xop->type = XTENSA_OP_L32R;
-		xop->imm = (int32_t)Value;
+		xop->imm = (int32_t)Xtensa_L32R_Value(MI, op_num);
 	} break;
 	case Xtensa_OP_GROUP_MemOperand: {
 		unsigned reg =

diff --git a/arch/Xtensa/XtensaMapping.h b/arch/Xtensa/XtensaMapping.h
@@ -10,6 +10,8 @@ typedef enum {
 #include "XtensaGenCSOpGroup.inc"
 } xtensa_op_group;
 
+int64_t Xtensa_L32R_Value(MCInst *MI, int op_num);
+
 void Xtensa_init_mri(MCRegisterInfo *mri);
 void Xtensa_printer(MCInst *MI, SStream *OS, void *info);
 bool Xtensa_disasm(csh handle, const uint8_t *code, size_t code_len,

diff --git a/tests/MC/Xtensa/l32r.yaml b/tests/MC/Xtensa/l32r.yaml
@@ -0,0 +1,25 @@
+test_cases:
+  - input:
+      bytes: [ 0x01,0x00,0x00 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a0, . -0x40000"
+  - input:
+      bytes: [ 0xf1,0x00,0x00 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a15, . -0x40000"
+  - input:
+      bytes: [ 0x01,0xff,0xff ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a0, . -0x4"