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Merge branch 'develop' of github.com:apollo-lhc/CM_FPGA_FW into develop
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dgastler committed Aug 9, 2023
2 parents 42ffa7a + 334005a commit 38d6f71
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Showing 3 changed files with 11 additions and 7 deletions.
5 changes: 2 additions & 3 deletions .ipbb_setup.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,12 @@ init:
- make list
- make prebuild_EMP_Cornell_rev1_p2_VU7p-1-SM_USP
- make address_table_EMP_Cornell_rev1_p2_VU7p-1-SM_USP
- make EMP_Cornell_rev1_p2_VU7p-1-SM_USP.tar.gz
- make prebuild_EMP_Cornell_rev1_p2_VU7p-1-SM_USP
- make address_table_EMP_Cornell_rev1_p2_VU7p-1-SM_USP
- make prebuild_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
- make address_table_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
- make EMP_Cornell_rev2_p1_VU13p-1-SM_USP.tar.gz
- make prebuild_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
- make address_table_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
- make EMP_Cornell_rev2_p2_VU13p-1-SM_USP.tar.gz


reset:
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5 changes: 5 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -192,3 +192,8 @@ make test :
#%.tar.gz : bit/top_%.svf kernel/hw/dtbo/ os/address_table/
%.tar.gz : bit/top_%.svf
@tar -h -zcf $@ $< -C kernel/hw/ dtbo -C ../address_tables address_table

EMP%.tar.gz : kernel/config_EMP%.yaml
$(MAKE) clean_overlays
$(MAKE) overlays
@tar -h -zcf $@ -C kernel/hw/ dtbo -C ../address_tables address_table
8 changes: 4 additions & 4 deletions configs/Cornell_rev1_p2_VU7p-1-SM_USP/config.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ AXI_CONTROL_SETS:


AXI_SLAVES:
V_IO:
F2_IO:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
Expand All @@ -32,7 +32,7 @@ AXI_SLAVES:
XML: "address_table/modules/VIRTEX_SYS_MGMT.xml"
UHAL_BASE: 0x80000000

V_CM_FW_INFO:
F2_CM_FW_INFO:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
Expand All @@ -59,7 +59,7 @@ AXI_SLAVES:
XML: "address_table/modules/IPBUS.xml"
UHAL_BASE: 0x85000000

V_C2C_INTF:
F2_C2C_INTF:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
Expand All @@ -79,7 +79,7 @@ AXI_SLAVES:
addr:
offset: "0xB3008000"
range: "4K"
irq_port: "V_C2CB/axi_c2c_s2m_intr_in"
irq_port: "F2_C2CB/axi_c2c_s2m_intr_in"
baud_rate: "115200"
axi_control: "${::AXI_MASTER_CTRL}"
manual_load_dtsi: "1"
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