Cmv12k remapper #34
Cmv12k remapper #34
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| # | 2 | 2 | 18 | | 4082 | | ||
| # | ... | | | | | | ||
| # | 7 | 15 | 31 | | 4095 | | ||
| # Note, that we have half as many output channels as input channels. We provide valid data on every clock cycle. (Almost, there will be some cycles where the data is not valid). |
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Can I haz some line wrapping for that?
| # Concretely this produces a pattern like this (for `n_channels = 8`) | ||
| # The sensor output is sturctured into bursts of 128 pixels, so we need to pay attention to the burst boundaries, as after a burst some overhead cycles take place | ||
| # channel written: | ||
| # | clock -> | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | |
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I do not understand what bram v is
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also why does this start with clock 2
| # And a single channel gets 1 pixel per clock cycle, for a total of 4096 / n_channel pixels. For example for 8 channels (per side): 512 pixels. | ||
| # This means we read out all of the 512 pixels in 32 cycles, so we can start the read out process with 32 pixels left. | ||
| # The next row will start soon after the first, so we store two rows and ping pong the buffers | ||
| # TODO(robin): this is fucked because of OH, no? |
| """Remaps one output port (if top and bottom outputs of the cmv12k are used, instantiate this twice!) to provide a linear output. | ||
| def __init__(self, input: ImageStream, n_bits=12, two_sided_readout=True): | ||
| assert two_sided_readout == True, "single sided readout is not supported" | ||
| assert n_bits == 12, "bit depth other than 12 is not supported" |
| class Cmv12kPixelRemapper(Elaboratable): | ||
| """Remaps one output port (if top and bottom outputs of the cmv12k are used, instantiate this twice!) to provide a linear output. | ||
| def __init__(self, input: ImageStream, n_bits=12, two_sided_readout=True): |
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why is the input an image stream though?
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and are input and output domains the same?
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yes, input and output domains are the same.
This is a ImageStream, because the cmv12k rx core outputs an ImageStream, I just built something that plugs into this.
But of course we could change this. We do not have a "clear" definition of ImageStream currently and the rx core also output line_last and frame_last, so it kind of makes sense to have its output be an ImageStream, but of course the pixel ordering is a bit "weird".
| wr_enable = Signal() | ||
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| # write address, write data and rea data is independent for each memory. | ||
| wr_address = [Signal(self.addr_width, name=f"wr_address_{i:02}") for i in range(self.n_mem)] |
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bikeshed: maybe we should rather store the ports here?
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Sure, don't have a strong feeling either way.
| # first step: double up the input words. We want to do this with as few FFs as possible. So | ||
| # we use the knowledge that we write the first fourth of channel immediately and only need to store a single pixel | ||
| # for the middle fourths we need to store two pixels, as we need to wait atleast one cycle more | ||
| # for the last forth we need to store three pixels, as a new one comes in before we can write the ol pixel data |
| channel_number = rd_address_delayed[bits_for(self.channel_block_size - 1) :] | ||
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| # for debugging | ||
| m.d.comb += Signal(16, name="channel_number").eq(channel_number) |
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Maybe do that directly above (as it also yields nicer rtlil?)
| @pytest.mark.parametrize("channels_per_side", [4, 8, 16, 32]) | ||
| def test_cmv12k_pixel_remapper(channels_per_side): | ||
| platform = SimPlatform() | ||
| # fixed for now |
| @@ -24,7 +24,8 @@ def __init__(self, filename=None): | |||
| caller_path = "" | |||
| stack = inspect.stack() | |||
| for frame in stack[1:]: | |||
| if "unittest" in frame.filename: | |||
| print(frame, frame.filename) | |||
This adds a remapper, that reorders the pixels coming from the cmv12k to follow the
ImageStreamconvention, though notably with more than a single pixel per cycle.Untested in hw, but tested in sim.