This repo will take you through different verilog projects
- MUX
- Counter
- Full adder
- Pipelining example
- NAND using CMOS(switch level)
- NOT using CMOS(switch level)
- BCD to 7-segment
- Priority Encoder
- Register Bank
-
Notifications
You must be signed in to change notification settings - Fork 2
Sahil-Udayasingh/Verilog
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
This repo will take you through different verilog projects
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published