arm64: dts: qcom: msm8937: Use smmu instead of iommu

Lanik123 · Dec 30, 2023 · f71733b · f71733b
1 parent 3b3fe12
commit f71733b
Showing 1 changed file with 39 additions and 27 deletions.
diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi
@@ -940,39 +940,51 @@
 			reg = <0x01937000 0x30000>;
 		};
 
-		apps_iommu: iommu@1e00000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			#iommu-cells = <1>;
-			compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
-			ranges = <0 0x01e20000 0x20000>;
+		apps_smmu: iommu@1e00000 {
+			compatible = "qcom,msm8937-smmu-500", "arm,mmu-500";
+			reg = <0x1e00000 0x40000>;
 
 			clocks = <&gcc GCC_SMMU_CFG_CLK>,
 				 <&gcc GCC_APSS_TCU_CLK>;
 			clock-names = "iface", "bus";
 
-			qcom,iommu-secure-id = <17>;
-
-			/* VFE */
-			iommu-ctx@14000 {
-				compatible = "qcom,msm-iommu-v1-ns";
-				reg = <0x00014000 0x1000>;
-				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-			};
+			#global-interrupts = <0>;
+			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 
-			/* MDP_0 */
-			iommu-ctx@15000 {
-				compatible = "qcom,msm-iommu-v1-ns";
-				reg = <0x00015000 0x1000>;
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-			};
+			qcom,iommu-secure-id = <17>;
 
-			/* VENUS_NS */
-			iommu-ctx@16000 {
-				compatible = "qcom,msm-iommu-v1-ns";
-				reg = <0x00016000 0x1000>;
-				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-			};
+			#iommu-cells = <2>;
 		};
 
 		adreno_smmu: iommu@1c40000 {
@@ -1039,7 +1051,7 @@
 					      "core",
 					      "vsync";
 
-				iommus = <&apps_iommu 0x15>;
+				iommus = <&apps_smmu 0x2800 0>;
 
 				ports {
 					#address-cells = <1>;