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Fix typo in CoreController Scala CI #40: Commit ccebc59 pushed by KasperHesse
February 23, 2024 12:10 1m 49s add_priv_mode
add_priv_mode
February 23, 2024 12:10 1m 49s
Rename HazardDetection -> CoreController Scala CI #39: Commit 11d0cb5 pushed by KasperHesse
February 23, 2024 10:52 1m 21s add_priv_mode
add_priv_mode
February 23, 2024 10:52 1m 21s
Add CSR support (#8) Scala CI #38: Commit f316330 pushed by KasperHesse
October 30, 2023 15:37 2m 54s main
main
October 30, 2023 15:37 2m 54s
Add CSR support Scala CI #37: Commit 91606dd pushed by KasperHesse
October 30, 2023 15:33 3m 1s add_csr_support
add_csr_support
October 30, 2023 15:33 3m 1s
Bump version to Chisel 5.0.0 (#7) Scala CI #36: Commit 1a2fc65 pushed by KasperHesse
October 11, 2023 12:02 2m 39s main
main
October 11, 2023 12:02 2m 39s
Fix broken tests on 5.0.0, update sbt version Scala CI #35: Commit 4589091 pushed by KasperHesse
October 11, 2023 10:13 2m 15s bump_version
bump_version
October 11, 2023 10:13 2m 15s
Bump to chisel 5.0.0 Scala CI #34: Commit 3027095 pushed by KasperHesse
October 9, 2023 11:17 1m 10s bump_version
bump_version
October 9, 2023 11:17 1m 10s
Update flow to simplify building and linking C programs (#6) Scala CI #33: Commit 03a89ca pushed by KasperHesse
September 28, 2023 14:41 1m 56s main
main
September 28, 2023 14:41 1m 56s
Update flow to simplify building and linking C programs Scala CI #32: Commit 919a53d pushed by KasperHesse
September 28, 2023 08:07 1m 56s make_c_better
make_c_better
September 28, 2023 08:07 1m 56s
Add wrapper around core for easier SoC implementation (#5) Scala CI #31: Commit 3e60b36 pushed by KasperHesse
September 24, 2023 15:23 2m 21s main
main
September 24, 2023 15:23 2m 21s
Add wrapper around core for easier SoC implementation (#5) Scala CI #30: Commit 3e60b36 pushed by KasperHesse
September 24, 2023 15:22 2m 28s master
master
September 24, 2023 15:22 2m 28s
Make tests more independent with distinct filenames Scala CI #29: Commit 0b977ea pushed by KasperHesse
September 22, 2023 14:22 1m 42s add_soc_wrapper
add_soc_wrapper
September 22, 2023 14:22 1m 42s
Tweak assembly compilation, remove printf-debugging Scala CI #28: Commit b330b6e pushed by KasperHesse
September 22, 2023 12:53 1m 2s add_soc_wrapper
add_soc_wrapper
September 22, 2023 12:53 1m 2s
Another attempt af fixing compilation issues Scala CI #27: Commit c483793 pushed by KasperHesse
September 22, 2023 08:16 1m 56s add_soc_wrapper
add_soc_wrapper
September 22, 2023 08:16 1m 56s
Fix compilation issues on linux Scala CI #26: Commit 392bc37 pushed by KasperHesse
September 20, 2023 16:40 1m 41s add_soc_wrapper
add_soc_wrapper
September 20, 2023 16:40 1m 41s
Add flowchart and FSM diagram of cache Scala CI #25: Commit 4e738fc pushed by KasperHesse
September 16, 2023 17:17 1m 56s add_cache
add_cache
September 16, 2023 17:17 1m 56s
Add Makefile, UART downloader, ysample programs that can be run on core Scala CI #24: Commit 7cbfd0c pushed by KasperHesse
September 16, 2023 17:16 1m 34s add_soc_wrapper
add_soc_wrapper
September 16, 2023 17:16 1m 34s
Add HW bootloader for loading program from UART Scala CI #23: Commit 6be4bcc pushed by KasperHesse
September 10, 2023 10:14 2m 24s add_soc_wrapper
add_soc_wrapper
September 10, 2023 10:14 2m 24s
Merge branch 'master' of https://github.com/KasperHesse/riscv-core Scala CI #22: Commit 9991c18 pushed by KasperHesse
September 10, 2023 10:12 2m 3s master
master
September 10, 2023 10:12 2m 3s
Fix memOp being true if instr in memory stage is invalid (#4) Scala CI #21: Commit 5822e4d pushed by KasperHesse
August 25, 2023 12:33 2m 5s master
master
August 25, 2023 12:33 2m 5s
Fix memOp being true if instr in memory stage is invalid Scala CI #20: Commit 9f38e72 pushed by KasperHesse
August 23, 2023 06:48 2m 7s fix_fml_errors
fix_fml_errors
August 23, 2023 06:48 2m 7s