pre-commit: autoupdate hooks #427

Fix regression introduced in 47e9e8c "security/tpm: replace CONFIG(TPMx) checks with runtime check": Replace BIOS_WARN with BIOS_WARNING. Change-Id: Id23cda2f5403effd2a4bda3852f0f300d0e62cdf Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81590 Reviewed-by: Elyes Haouas <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Fixes error "Cache as RAM area is too full" during compilation of apu2. Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

- Remove unused CONSOLE region - Shrink BOOTSPLASH to 512K - Increase WP_RO by 512K Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I9efdf2e87562cb528248e24ab694a694f23a00b5 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I407ed63b2388e04d8d33967f8e13be3f6d3530f5 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I433dfcef9d1cf8f34299a16e0478edfbfe5ae717 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: If9257ef9a86260f185e58cedb457d68487648f8e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ic083a7a0207366a8d3b18042fecaedc86b43fe13 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I1a04090c541035adee4b47417e1379daf672f666 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Idb06108f9309a51ef719ad81b88c07146050a591 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I25347fea761f858fb565fbfe3f528dbfe8d09381 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I5c8d8398e649cb7a418b1d77c39e38fcc8e811d5 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ie2f9717f57af8f5de00febe2643da7518e7d8cd7 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Idf5ca08834f568052c2d67e1a9f1f40008fc2025 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I6bdfe3c88ecaf2930910cd9e4915710cd0eb15d2 Signed-off-by: Michał Kopeć <[email protected]>

Retry calling the SMI 5 times in case the initial write to APM did not cause SMM entry immediately. Fixes occasional SMMSTORE initialization failure on Clevo NV4xPZ with Intel i5-1240P processor. The issue was especially evident when all logging in coreboot was disabled. Based on SMMSTORE implementation in MrChromebox's fork of EDK2: MrChromebox/edk2@27854bc Change-Id: I8929af25c4f69873bbdd835fde5cb60fc324b6ab Signed-off-by: Michał Kopeć <[email protected]>

…a PMC Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

…access Signed-off-by: Michał Żygowski <[email protected]>

…le GPIO Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

…anifests Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

…for devices Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

… built in UART Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Change-Id: I14ca3ae6fd63d95637704d9be16660336b9248da Signed-off-by: Michał Kopeć <[email protected]>

…store Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Change-Id: I7f2c9f756102ad6e63d8aafd3013003d31676ce4 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: If44057ec1a56afb5f1d467a42dad98bde8cb8551 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I0eb2ae2b1a65fc4393696eb0ec73cfbe6596b21b Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I625c566f1a5e2653338cf8e8ff6217089459215c Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: If7dde844e1b69be92685e0c33fb2cbba37eb33ea Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ib26c51973e09fe39f07fc9a79f812adb0d58ac06 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I4b5a6bb0687184d5e05d237b09dcd3561553ba0d Signed-off-by: Michał Kopeć <[email protected]>

Full decompressed EC (128K) doesn't fit into the default CBFS cache size (16K). So bump the size to twice of what we need here. Change-Id: I21e01d0dfb0e2221d5d5f4bf0656e27561df0e06 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I105c11306181a403b44a0aed3079d00cadfa813e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I10b8b45a85e922daf05d0f0f985a39488ea2119e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I1f3ac59d15cbb5013605bfcf2333634e664f4028 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I121c71294ac2a8ee2e3ca6027285e4c5ac19bfa7 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Icce4ae7cb674b9ce0833d7d1167ecdd31125780e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ia29d4a34f3eafa177125c553680f1e4789c96055 Signed-off-by: Michał Kopeć <[email protected]>

Intel platforms may support more than one watchdog, and the TCO watchdog is not always operable due to different strappings. Move the TCO watchdog specific code to the appropriate block to allow SoCs or platforms to choose their preferred watchdog implementation. TEST=Build Protectli vault_cml with SOC_INTEL_COMMON_BLOCK_TCO_WDT_WDAT selected. Change-Id: I119f0fafcf2452fe3cbab4a68bc342121032550c Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I5b0cabdb9d50b202296014a86b3e727c9bd93b8f Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I5b936f26db575abf38170bd4b5ce6e126d85dfd3 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I1b474a8e5068f32cd0d7c8c132914572addaaeb9 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I4801ff97d13dc9dae997f2dbc2092a589717716c Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I632316e621838d4578a7de718fe5246b99407a56 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I57963d3de1a53f75952cbe8efc38da63bf1c64fd Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I0e6acec166744b469230053bfe1be79c1fe30354 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I26ba2dbde0558eb895798c33a2ed71c76919f271 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I95a2b971b2ae16ce5593944a7a6fceb325cc13a0 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Iaa0dd3660aa64cb5a21fd632679056fee27fcc3e Signed-off-by: Michał Kopeć <[email protected]>

needed at least on alderlake for correct operation Change-Id: Idcf5ce66248c0486bc2ea7242c75c6b824c82b75 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I95b09487808747f9a88fc82477581cdb6086136e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I071e5cd142df352e46f86087d2e9a0d95ea827dc Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I18775bfc4a154942a7fecc2a26c6ebf2210f5579 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ibab018019815db7f3bfcbb2031cb9af0a196b28a Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I2b10008f3f09370b209534c9125e5645003258f8 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: If8400779d79eba9b4b56ad9df718528742364a9e Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ia242f3eecce30248f1f097960ae5efe09c87baa8 Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Fixes MemoryInit on the newest hardware revision. Signed-off-by: Michał Żygowski <[email protected]>

Avoid tpm_config_t type redefinition by adding crb and pc80 prefixes. TEST=Compile MSI PRO Z690-A target with CRB and PC80 TPM chips enabled in devicetree. Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12 Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

HWP is too aggressive in power savings and does not let using full bandwidth of Ethernet controllers without additional stressing of the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). Let the Linux use acpi-cpufreq governor driver instead of intel_pstate by disabling HWP. Signed-off-by: Michał Żygowski <[email protected]>

This function isn't used anywhere. It probably wouldn't work with current coreboot anyway, as it identity mapped lower 2GB of RAM, while ramstage is run from CBMEM, which is usually just below top of memory. It was last used in K8 code that is long gone. Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c Signed-off-by: Krystian Hebel <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Sergii Dmytruk <[email protected]>

This function had roughly the same use (except PAT) as part of memset_pae(), however the latter is able to make use of PAE and map physical memory located above 4 GB. Remove paging_identity_map_addr() to avoid semi-duplicated code. The function has been unused since CB:26745. Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8 Signed-off-by: Krystian Hebel <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>

The code used to reserve MEMSET_PAE_PGTL_SIZE (20 KiB) for page used for clearing the memory above 4 GiB that was assumed to be 2 MiB page. memset_pae() checks only the alignment and not the size of this region, so no error was reported by it. In most cases this reserved memory in 2-4 MiB range, and because this range isn't usually used by coreboot (architectural stuff is located in lower 1 MiB, coreboot tables and ramstage are close to TOLUM and payload isn't yet loaded when the broken code is executed), it never caused any problems. Change MEMSET_PAE_PGTL_SIZE to MEMSET_PAE_VMEM_SIZE and fix wrong macro definition to reserve properly sized region. Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3 Signed-off-by: Krystian Hebel <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82397 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Sergii Dmytruk <[email protected]> Reviewed-by: Paul Menzel <[email protected]>

Code dealing with PAE can be used outside of memset_pae(). This change extracts creation of identity mapped pagetables to init_pae_pagetables() and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c. MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply only to memset_pae(). Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb Signed-off-by: Krystian Hebel <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

HWP is too aggressive in power savings and does not let using full bandwidth of Ethernet controllers without additional stressing of the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). Let the Linux use acpi-cpufreq governor driver instead of intel_pstate by disabling HWP. Porting a change from VP2420 in: d10fe79 Change-Id: I81cb4cd64a635e8835d95c89af715927d5902f94 Signed-off-by: Maciej Pijanowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

The ath10k_pci driver in Linux constantly reports AER errors. It seems the Atheros cards do not like AER. Disable it to avoid warnings in dmesg. Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Incorrectly assigned TPM family to the input parameter in pc80_tpm_probe could lead to disablign the TPM driver in ramstage. As a result the TPM ACPI code would not be generated, TPM not properly started and OS/payload not recognizing the TPM. Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Change-Id: I7605c09b692a94dec6bd6d55b394945ee2a4ec64 Signed-off-by: Sergii Dmytruk <[email protected]>

Change-Id: Ide818b9e064286bc52dcdacb9c2984216e2981a0 Signed-off-by: Sergii Dmytruk <[email protected]>

Depending on how firmware image was passed to QEMU, it may behave as: - ROM - memory mapped reads, writes are ignored (FW image mounted with '-bios'); - RAM - memory mapped reads and writes (FW image mounted with e.g. '-device loader'); - flash - memory mapped reads, write and erase possible through commands. Contrary to physical flash devices erase is not required before writing, but it also doesn't hurt. Flash may be split into read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd. Combined size of system firmware must not exceed 8 MiB by default (FW image(s) mounted with '-drive if=pflash'). This function detects which of the above applies and fills region_device_ops accordingly. Tested by starting QEMU with firmware passed as '-drive if=pflash', '-drive if=pflash,readonly=on' and '-bios'. When started with firmware passed through '-device loader', coreboot complains about corrupted FMAP, but this is the same behavior as without this change: [ERROR] Invalid FMAP at 0x40000 [EMERG] Cannot locate primary CBFS Writable pflash support was added about 17 years ago, so it should be supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with default IO APIC memory range. Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Signed-off-by: Krystian Hebel <[email protected]>

qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating Intel chipset. In addition, even though it implements SMI_STS register, QEMU never sets any bits in it. As there is little emulated hardware that can be generating SMI, assume that all SMIs come from APM. This source is used e.g. to disable ACPI (which wasn't working until now on QEMU) and SMMSTORE. Tested by invoking SMMSTORE commands from the payload with SMM logging. Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f Signed-off-by: Krystian Hebel <[email protected]>

By default, QEMU bails when trying to use bigger images mounted with '-drive if=pflash', which is required to make use of writable flash introduced in CB:82555. This changes both default size in Kconfig as well as FMAP layouts. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with IO APIC memory range. Default is still 8 MiB, so it makes sense to have identical default in coreboot. Error thrown by QEMU when trying to use too big ROM: qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Signed-off-by: Krystian Hebel <[email protected]>

Commit c2830c9 ("acpi.c: Add XSDT on QEMU") added code that copied RSDT to XSDT since QEMU doesn't generate the latter. However, this new code didn't move 'current' pointer forward if XSDT pointer was already non-zero, such as after warm reset. As a result, SSDT was written in place of XSDT, which resulted in panic in edk2 after a reboot. This change covers SSDT generation with the same check for existing XSDT address as is used for tables generated by QEMU. To test, build coreboot with debug edk2 payload, boot to UEFI shell and reboot with `reset` command. Without this change, edk2 panicked in AcpiTableDxe. Command line used for testing: qemu-system-x86_64 -machine q35,smm=on \ -drive if=pflash,format=raw,unit=0,file=build/coreboot.rom \ -serial stdio Change-Id: I7f38467b7de3f35fc3ec3854a840de8345cd0fe5 Signed-off-by: Krystian Hebel <[email protected]>

This allows conditional inclusion of drivers in edk2 proper depending on whether edk2-platforms is used or not. Change-Id: I53b16f9b400cd7a5ea585b16bf9693ac46777ab0 Signed-off-by: Krystian Hebel <[email protected]>

Change-Id: Ic7e9835f557df4b2f248faeb04f2f16185737ad4 Signed-off-by: Krystian Hebel <[email protected]>

This config enables all currently available Dasharo menus, even if they don't work for QEMU. It may be used for testing or demonstration purposes. Only OC WDT is disabled, as enabling it results in build failing on no value specified for PcdOcWdtTimeoutDefault. Change-Id: I08ee0fd078056c77e7b7bfbdb2bab0a459c6e822 Signed-off-by: Krystian Hebel <[email protected]>

Change-Id: If4b9cd5d2c4a60b4f400610305d6984f5ebae6c1 Signed-off-by: Krystian Hebel <[email protected]>

Signed-off-by: Krystian Hebel <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

The TCC offset occupies bits 29:24 of the TEMPERATURE_TARGET, so the mask should be. Confirmed on SKL and onwards, APL and GLK. Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

futility always prints a warning when building: WARNING: prepare_slot: VBLOCK_A keyblock is invalid. This is the expected state, because at that point vblock hasn't been created yet. Pipe warnings to /dev/null to prevent worrying users unnecesarily. This workaround should be removed once upstream accepts this patch: https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_reference/+/5682443 Change-Id: I93fd5dafe220bafcf5325ecd4f9f4ee94fc3f81f Signed-off-by: Michał Kopeć <[email protected]>

The board does not support SATA disks. Despite the M.2 slots have the SATA lines, the silicon does not support the dynamic switching between SATA and PCIe. Disable the SATA controller to make Windows happy, as the straps are set for PCIe lanes. Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Pawel Langowski <[email protected]> Signed-off-by: Maciej Pijanowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Filip Gołaś <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Co-authored-by: Krystian Hebel <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Print key hashes as it may be useful when obtaining information from binary about the used keys and what hash should be provisioned in TXE. Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Co-authored-by: Krystian Hebel <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

…g definitions Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

iPXE configuration of the boards were broken after a rebase, so this also involved setting CONFIG_BUILD_IPXE=y which now enables the build of iPXE. Change-Id: Ib2af25f7259c31f2e89dc10f473331733c255796 Signed-off-by: Sergii Dmytruk <[email protected]>

Change-Id: I9be3d920db15a755b7616a1d6fab5dc390bb6f0c Signed-off-by: Sergii Dmytruk <[email protected]>

Change-Id: I542a11ed2e2bad0bec3012b1a8227fb137528854 Signed-off-by: Sergii Dmytruk <[email protected]>

Standard and extended sets of tests, without the "unstable" ones. Change-Id: I4d2fc253a0e2434aecf48ae11ba49fa2b753d4fa Signed-off-by: Sergii Dmytruk <[email protected]>

Commit 05adc35 pointed EDK2 revision at a commit that's not pulled by `git clone` (comes from a removed or force-pushed branch) resulting in a non-buildable EDK2 checkout. Change-Id: Ie4eaa45667d3b1643bf734a9984f212d6dca505c Signed-off-by: Sergii Dmytruk <[email protected]>

`git rev-parse reference` doesn't fail on unknown commit hash unless something like `^{object}` is appended (`^{commit}` can probably be used as well). Change-Id: I7ef39aeee2e902ac2fad6ac41b546c47418e1dec Signed-off-by: Sergii Dmytruk <[email protected]>

Change-Id: Ief5292d59af43b4f6ccda31c188a089ce3c6216f Signed-off-by: Sergii Dmytruk <[email protected]>

This is to allow customizing flash map when vboot isn't used. Change-Id: I935b06db62f930e48a801f3aafd101767e04b223 Signed-off-by: Sergii Dmytruk <[email protected]>

To support custom boot splash image. Change-Id: Ied86aa3f372bb9752ef58b0d291e453f9dd75e7c Signed-off-by: Sergii Dmytruk <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Change-Id: I5fde994b9dc05469b08c6a14ecd6b971a25e365f Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I0626867dc882e77b1b5018b0851ca9a2c9e57ff0 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I161febbca12cd116a27167138a6ab523a644763c Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I500f4b502e1ac58e437e53bd0e4cb934c7bb3bbc Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ib7c537a1e94fdeaabc65fcabeee17fff8a0e753a Signed-off-by: Michał Kopeć <[email protected]>

Needed for Windows not to BSOD due to malformed ACPI tables. Change-Id: Id8a8acea43d0d4615fb26ed66fddda2e74ca0f28 Signed-off-by: Michał Kopeć <[email protected]>

… option Change-Id: I91d2133bf6a9f2f9ca355f1af2c0d454795d6ef8 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I082a4459afd80c328c9233b37ddd6f3a2c5bc528 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I16f20956a1490da02acc24156360aef235111494 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I2e05a6f76308b8b89ec9279888ae9fc6a80152a0 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I4c6655eda6729f2c12f99a09174da6ebc2795258 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I820044e39d161c5c993d2cd6bb51bcb56eb9e9ba Signed-off-by: Michał Kopeć <[email protected]>

Add Clevo V5x0TU mainboard. Preliminary support for the dGPU variant (V5x0TNx) is also added, but full support will be added in subsequent patches. Change-Id: Ic4ffba29e50b6bf2ee010d798f7a952d1264f15c Signed-off-by: Michał Kopeć <[email protected]> Co-authored-by: Michał Żygowski <[email protected]> Co-authored-by: Filip Gołaś <[email protected]>

The submodules are updated in subsequent steps anyway. Change-Id: I4243ae3862c89306d355c9559708b22cb86f4d44 Signed-off-by: Michał Kopeć <[email protected]>

Set the L1 substate optimize register to 0xF, like Insyde does. I don't know what exactly that does, but it works :D Change-Id: I833e2478cccff4c7f711f1b0614c5fcb6513aafa Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I39529022821f96bfee6aaaee9cc86072c90393a2 Signed-off-by: Michał Kopeć <[email protected]>

Silences a warning from fwupd when booting with EDK2 payload. Change-Id: I9c7e1f76c1833476b0f88e5a40e888a1721eb1b3 Signed-off-by: Michał Kopeć <[email protected]>

…dorcode Change-Id: If7203621e7767bae8ad791947e61e5aefb31bc19 Signed-off-by: Michał Kopeć <[email protected]>

…older Change-Id: I780f662d5df516cc46fa6b4ac180e8cbb1c8c8e8 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I56f3cfdeb2bfc4f07e4595009fa89acbf048da92 Signed-off-by: Michał Kopeć <[email protected]>

The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented in non-Lite CSE SKUs. TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 34,000 945:CSE started to handle ICC configuration 172,000 (138,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000) 991:Die Management Unit (DMU) load completed 360,000 (46,000) 0:1st timestamp 385,844 (25,844) 11:start of bootblock 398,796 (12,952) 12:end of bootblock 402,099 (3,302) [...] Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Signed-off-by: Michał Kopeć <[email protected]>

DDR5 uses a Serial Presence Detect (SPD) with hub function (SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`). Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Co-authored-by: Meera Ravindranath <[email protected]> Signed-off-by: Jeremy Soller <[email protected]> Signed-off-by: Tim Crawford <[email protected]>

Apply CB:75284 to Meteor Lake. CB:52731 introduced support for reading SPD from the EEPROM via SMBus. Replace the now unneeded workaround for DDR5 with filling in the correct channels for DDR5. Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386 Signed-off-by: Jeremy Soller <[email protected]> Signed-off-by: Tim Crawford <[email protected]>

Change-Id: Ibc4e00dec9953a426d8dacf87f3a09c57a80d9e6 Signed-off-by: Michał Kopeć <[email protected]>

CSE will not respond to EOP in Debug mode. Change-Id: Ifba407c52c6384ca7932ce353b1a66d4da3f6661 Signed-off-by: Michał Kopeć <[email protected]>

Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <[email protected]>

This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>

Introduce a function to determine whether the number of cache sets is a power of two. This aligns with common cache design practices that favor power-of-two counts for efficient indexing and addressing. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified functionality on google/ovis and google/rex (including a non-power-of-two Ovis configuration). Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>

This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>

Change-Id: I702013a6532534bf4fffa824bfd8e4a550abdd3a Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ia3c6a35e5b37fb1a33cbf69c177b37298e04321e Signed-off-by: Michał Żygowski <[email protected]>

Caching the RAMTOP causes issues with FSP MemoryInit for platforms with DIMM modules. When memories are swapped, the training may sometimes hang randomly. Seems to be a manifestation of the issue described here: https://review.coreboot.org/c/coreboot/+/81269/ (despite the L3 cache sets is power of 2 on the tested i5-1235U SKU). Disabling the RAMTOP caching make the memory training reliable no matter how many times the DIMM modules are swapped/changed in slots. RAMTOP was designed primarily for boot time optimizations in mind (most likely for Chromebooks), so disable the RAMTOP caching for all non-ChromeOS builds to boot reliably. Signed-off-by: Michał Żygowski <[email protected]>

This is a workaround for modules that don't correctly populate the serial number field in SPD. When such modules are swapped, they generate the same CRC, causing FSP to mistakenly consider them the same, and attempt to restore cached MRC settings. This won't work when the modules are different. As a workaround, force retrain the memory when RTC failure is detected. Users are expected to reset their CMOS upon changing memory modules. Change-Id: Iebb2810914b728317ce5ebd84b61667d2ba10529 Signed-off-by: Michał Kopeć <[email protected]>

Doesn't work with any FSP revs tested so far. Change-Id: Ifd112230cdfc645e68f2146677008b200ae1b0a3 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Iae4bb0965aee8dad819320570b1852939a6ecab7 Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I4843ed215bff8a003799b399885950e69d1daf4d Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I16517f3b76cf706650adafbe38af1d280b4d2f3d Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

…le lines Rationale: coreboot coding style guidelines Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Rename to page_ptr which more closely aligns with the SPD5 spec. Signed-off-by: Michał Kopeć <[email protected]>

Reduce amount of nested if statements by adding separate branches for DDR5, DDR4 and older SPD variants. Signed-off-by: Michał Kopeć <[email protected]>

DDR5 SPD page length is 1024 bytes. Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

This change fixes building NovaCustom V540TU, which previously errored out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition. Replace soc/gpio_defs.h with gpio.h which includes everything we need, same as it was done for ADL in change 71266, and other SoCs. TEST=Build and boot NovaCustom V540TU Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Sebastian Czapla <[email protected]>

updates: - [github.com/pre-commit/pre-commit-hooks: v4.4.0 → v5.0.0](pre-commit/pre-commit-hooks@v4.4.0...v5.0.0) - [github.com/talos-systems/conform: v0.1.0-alpha.27 → v0.1.0-alpha.30](siderolabs/conform@v0.1.0-alpha.27...v0.1.0-alpha.30)

pre-commit: autoupdate hooks #427

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pre-commit: autoupdate hooks #427

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