diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c index 37edd3dacad..f539ace5270 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c @@ -17,6 +17,9 @@ enum { +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif #ifdef BSP_USING_SPI3 SPI3_INDEX, #endif @@ -55,6 +58,20 @@ struct lpc_spi static struct lpc_spi lpc_obj[] = { +#ifdef BSP_USING_SPI1 + { + .LPSPIx = LPSPI1, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCOMM1, + .clock_div_name = kCLOCK_DivFlexcom1Clk, + .clock_name = kCLOCK_FroHf, + .tx_dma_request = kDmaRequestMuxLpFlexcomm1Tx, + .rx_dma_request = kDmaRequestMuxLpFlexcomm1Rx, + .DMAx = DMA0, + .tx_dma_chl = 0, + .rx_dma_chl = 1, + .name = "spi1", + }, +#endif #ifdef BSP_USING_SPI3 { .LPSPIx = LPSPI3, diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig index ef479082e0d..c97957a5e2a 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig @@ -60,6 +60,10 @@ menu "On-chip Peripheral Drivers" default y if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable Flexcomm1 as SPI" + default n + config BSP_USING_SPI3 bool "Enable Flexcomm3 as SPI" default n @@ -187,7 +191,31 @@ endmenu menu "Board extended module Drivers" - + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select BSP_USING_SPI1 + select PKG_USING_RW007 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config BOARD_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi1" + + config BOARD_RW007_CS_PIN + hex "CS pin index" + default 27 + + config BOARD_RW007_INT_BUSY_PIN + hex "INT/BUSY pin index" + default 10 + + config BOARD_RW007_RST_PIN + hex "RESET pin index" + default 28 + endif endmenu endmenu diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c index 0ce94a76944..e6d3e1c8f45 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c @@ -1,4 +1,4 @@ - +#include "rtconfig.h" #include "fsl_common.h" #include "fsl_port.h" @@ -43,17 +43,27 @@ void BOARD_InitBootPins(void) PORT0->PCR[6] = PORT_PCR_MUX(12) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* CLKOUT */ +#ifdef BSP_USING_I2C1 PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SDA */ PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SCL */ +#endif PORT0->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SDA */ PORT0->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SCL */ -// PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_0 */ -// PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_1 */ -// PORT0->PCR[26] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_2 */ -// PORT0->PCR[27] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_3 */ +#ifdef BSP_USING_SPI1 + /* Arduino D11(P0_24), D12(P0_26), D13(P0_25) as SPI function, for RW007 MOSI, MISO, CLK */ + PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_24: FC1_0 */ + PORT0->PCR[26] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_26: FC1_2 */ + PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_25: FC1_1 */ + + /* Arduino D8(P0_28), D9(P0_10), D10(P0_27) as GPIO function, for RW007 RST, INT, CS */ + /* drv_pin.c works well, follow lines just notice that pins we used as GPIO function */ + // PORT0->PCR[28] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_28: P0_28 */ + // PORT0->PCR[10] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_10: P0_27 */ + // PORT0->PCR[27] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_27: P0_27 */ +#endif /* PMOD */ PORT1->PCR[0] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_0 SDO/D[0], FC3_SPI_MOSI */