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Refine thermal model with inductive load #42

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pattacini opened this issue May 19, 2023 · 3 comments
Open

Refine thermal model with inductive load #42

pattacini opened this issue May 19, 2023 · 3 comments
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domain-modeling Pertains to model-based design team-fix Activity performed by Team FIX type-board-amcbldc Relevant to the AMCBLDC development

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@pattacini
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          A F2F chat with @pattacini and @maggia80 highlighted that it is important to consider how the PWM signal is generated (whether it is in Left-aligned mode or Center-aligned), and how the current is measured.

Since we are dealing with an inductive load, we need to consider exponential transitory effect, during which the PWM signal of a phase is positive.
The current is measured in the middle of the positive PWM, during which the transitory might not be exhausted. This depends on the time constant (Phase resistance and inductance), and on the duty cycle.

Therefore accounting for the electrical transitory period might be the key to improve the model and reduce the performance discrepancy in continuous current (aka Iq in the case above).

Support material:

Originally posted by @mfussi66 in #36 (comment)

@pattacini pattacini added team-fix Activity performed by Team FIX domain-modeling Pertains to model-based design type-board-amcbldc Relevant to the AMCBLDC development labels May 19, 2023
@pattacini
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Hi @fgarini,

We would need your help to get to know how the PWM is actually generated in our AMCLBDC board to better organize in view of the OP.

cc @andreaderito @maggia80 @Nicogene @mfussi66

@fgarini
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fgarini commented May 19, 2023

Ciao, in the amc_bldc the PWM generation is center-aligned.
I attach the detailed configuration mainly to orient myself, here is some the data:
image
image

The frequency of the PWM is 168MHz/[2(up-down counting)*(1023+1)] = 82KHz

The ADC in use is the 2nd channel and the conversion is triggered by tim1 6th channel, also called oc6ref- TRGO2.
(tim1 configuration)
image
image
(adc2 configuration)
image

For each PWM cycle one ADC conversion will be triggered in sequence, meaning that for each phase the sample period for each ADC current channel is 82/3 = 27.3KHz
Side note: The ADC has a silicon bug that requires to execute two consecutive conversions and discard the second one, for each phase.

The conversion is triggered at the 831th of the 1024 pulse counts, in order to stay at a reasonable safe distance from the commutations - it is supposed that when you have a motor with nominal 24V and the board that is supplied with 32V or more more, it will likely have a sensible lower PWM period.

image

Other useful information is written by Giorgio in the user manual contained in the repo amc_bldc\docs

@fgarini
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fgarini commented May 19, 2023

I completed the comment above. Let me add a few considerations: the motor IIT code 15562 has a quite high L/R constant with respectively 3,15mH and 25.9Ohm = 122uS
the PWM period is (1/82kHz) = 12uS.

Even in short circuit with a full-period PWM applied, the actual delta in the current current would be:

$$I=I_{0}(1−e^{−t/τ}) \\$$

With 42V and 25.9Ohm, I0 is 1.62A
The dI is: [1.62A * (1-e^{-12uS/122uS)] = [1.62A * 0,094] = 0.15A.
I did very conservative the calculations, since i put the condition of short circuit with no initial current, simultaneously applying the maximum charge voltage for the whole sample period.

In addition to that I don't find critical the settling time/step response of the current sensor ACS70331, that is nominally less than 550ns
image

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domain-modeling Pertains to model-based design team-fix Activity performed by Team FIX type-board-amcbldc Relevant to the AMCBLDC development
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