From 2c68135d28c12114e096f3497379b3de5e6838e4 Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Thu, 20 Apr 2023 15:40:44 +0800 Subject: [PATCH 1/7] RISCV: Add vector psabi checking. This patch adds support to check function's argument or return is vector type and throw warning if yes. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_vector_psabi_warnning): (riscv_arg_has_vector): (riscv_pass_in_vector_p): (riscv_get_arg_info): gcc/testsuite/ChangeLog: * gcc.target/riscv/vector-abi-1.c: New test. * gcc.target/riscv/vector-abi-2.c: New test. * gcc.target/riscv/vector-abi-3.c: New test. * gcc.target/riscv/vector-abi-4.c: New test. * gcc.target/riscv/vector-abi-5.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv.cc | 62 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++++ gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 +++++ gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++++ gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++++ gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++++ 6 files changed, 135 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 76eee4a55e9..c15969ff121 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3728,6 +3728,65 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, GEN_INT (offset2)))); } +static void +riscv_vector_psabi_warnning () +{ + warning (OPT_Wpsabi, "ABI for the vector type is currently in experimental" + "stage and may changes in the upcoming version of GCC."); +} + +static bool +riscv_arg_has_vector (const_tree type) +{ + bool is_vector = false; + + switch (TREE_CODE (type)) + { + case RECORD_TYPE: + if (!COMPLETE_TYPE_P (type)) + break; + + for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) + if (TREE_CODE (f) == FIELD_DECL) + { + if (!TYPE_P (TREE_TYPE (f))) + break; + + if (VECTOR_TYPE_P (type)) + is_vector = true; + else + is_vector = riscv_arg_has_vector (TREE_TYPE (f)); + } + + break; + + case VECTOR_TYPE: + is_vector = true; + break; + + default: + is_vector = false; + break; + } + + return is_vector; +} + +/* Pass the type to check whether it's a vector type or contains vector type. + Only check the value type and no checking for vector pointer type. */ + +static void +riscv_pass_in_vector_p (const_tree type) +{ + static int warned = 0; + + if (type && riscv_arg_has_vector (type) && !warned) + { + riscv_vector_psabi_warnning (); + warned = 1; + } +} + /* Fill INFO with information about a single argument, and return an RTL pattern to pass or return the argument. CUM is the cumulative state for earlier arguments. MODE is the mode of this argument and @@ -3812,6 +3871,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, } } + /* Only check existing of vector type. */ + riscv_pass_in_vector_p (type); + /* Work out the size of the argument. */ num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant (); num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c new file mode 100644 index 00000000000..114ee6de483 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +void +fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c new file mode 100644 index 00000000000..fd4569535cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +vint32m1_t +fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c new file mode 100644 index 00000000000..844a5db4027 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +vint32m1_t* +fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c new file mode 100644 index 00000000000..f9575f26786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +typedef int v4si __attribute__ ((vector_size (16))); + +v4si +fun (v4si a) { return a; } /* { dg-warning "the vector type" } */ + +void +bar () +{ + v4si a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c new file mode 100644 index 00000000000..9b80fb9f846 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" +typedef int v4si __attribute__ ((vector_size (16))); + +v4si* +fun (v4si* a) { return a; } /* { dg-bogus "the vector type" } */ + +void +bar () +{ + v4si a; + fun (&a); +} From 211f26b29e70023d694a851317a8c01e3cbbb5ee Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Sun, 23 Apr 2023 20:37:48 +0800 Subject: [PATCH 2/7] fix: disable the warning on attribute vector_size. --- gcc/config/riscv/riscv.cc | 25 +++++++++++++------ gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 2 +- gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 10 ++++---- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index c15969ff121..50de8d09dbd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3728,11 +3728,18 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, GEN_INT (offset2)))); } -static void -riscv_vector_psabi_warnning () +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and + intrinsic vector type. Because we can't get the decl for the params. */ + +static bool +riscv_arg_has_vector_size_attribute(const_tree type) { - warning (OPT_Wpsabi, "ABI for the vector type is currently in experimental" - "stage and may changes in the upcoming version of GCC."); + tree size = TYPE_SIZE(type); + if (size && TREE_CODE(size) == INTEGER_CST) + return true; + + /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ + return false; } static bool @@ -3752,8 +3759,9 @@ riscv_arg_has_vector (const_tree type) if (!TYPE_P (TREE_TYPE (f))) break; - if (VECTOR_TYPE_P (type)) - is_vector = true; + /* If there's vector_size attribute, ignore it. */ + if (VECTOR_TYPE_P (TREE_TYPE (f))) + is_vector = !riscv_arg_has_vector_size_attribute (type); else is_vector = riscv_arg_has_vector (TREE_TYPE (f)); } @@ -3761,7 +3769,7 @@ riscv_arg_has_vector (const_tree type) break; case VECTOR_TYPE: - is_vector = true; + is_vector = !riscv_arg_has_vector_size_attribute (type); break; default: @@ -3782,7 +3790,8 @@ riscv_pass_in_vector_p (const_tree type) if (type && riscv_arg_has_vector (type) && !warned) { - riscv_vector_psabi_warnning (); + warning (OPT_Wpsabi, "ABI for the vector type is currently in experimental" + "stage and may changes in the upcoming version of GCC."); warned = 1; } } diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c index f9575f26786..a5dc2dffaac 100644 --- a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c @@ -6,7 +6,7 @@ typedef int v4si __attribute__ ((vector_size (16))); v4si -fun (v4si a) { return a; } /* { dg-warning "the vector type" } */ +fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */ void bar () diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c index 9b80fb9f846..1fe83c8fc87 100644 --- a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c @@ -1,15 +1,15 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64d" } */ -#include "riscv_vector.h" typedef int v4si __attribute__ ((vector_size (16))); +struct A { int a; v4si b; }; -v4si* -fun (v4si* a) { return a; } /* { dg-bogus "the vector type" } */ +void +fun (struct A a) {} /* { dg-bogus "the vector type" } */ void bar () { - v4si a; - fun (&a); + struct A a; + fun (a); } From 10043818ab6d879eb9bf16909165d9b357871c3f Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Sun, 23 Apr 2023 20:44:37 +0800 Subject: [PATCH 3/7] fix: code style. --- gcc/config/riscv/riscv.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 50de8d09dbd..838c8915965 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3732,10 +3732,10 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, intrinsic vector type. Because we can't get the decl for the params. */ static bool -riscv_arg_has_vector_size_attribute(const_tree type) +riscv_arg_has_vector_size_attribute (const_tree type) { - tree size = TYPE_SIZE(type); - if (size && TREE_CODE(size) == INTEGER_CST) + tree size = TYPE_SIZE (type); + if (size && TREE_CODE (size) == INTEGER_CST) return true; /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ From f9bafb83f6f2bc0542e1660ebd9f707a6360f9f0 Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Mon, 24 Apr 2023 10:16:12 +0800 Subject: [PATCH 4/7] fix: need to split the words with space. --- gcc/config/riscv/riscv.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 838c8915965..d93edd60c23 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3790,8 +3790,9 @@ riscv_pass_in_vector_p (const_tree type) if (type && riscv_arg_has_vector (type) && !warned) { - warning (OPT_Wpsabi, "ABI for the vector type is currently in experimental" - "stage and may changes in the upcoming version of GCC."); + warning (OPT_Wpsabi, "ABI for the vector type is currently in " + "experimental stage and may changes in the upcoming version of " + "GCC."); warned = 1; } } From cb6ae981908fc28fdf9183428494da09593dc192 Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Mon, 24 Apr 2023 14:55:14 +0800 Subject: [PATCH 5/7] fix: pass the right field type and other comments. --- gcc/config/riscv/riscv.cc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d93edd60c23..6ff33abb75f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3732,7 +3732,7 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, intrinsic vector type. Because we can't get the decl for the params. */ static bool -riscv_arg_has_vector_size_attribute (const_tree type) +riscv_scalable_vector_type_p (const_tree type) { tree size = TYPE_SIZE (type); if (size && TREE_CODE (size) == INTEGER_CST) @@ -3756,20 +3756,21 @@ riscv_arg_has_vector (const_tree type) for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) if (TREE_CODE (f) == FIELD_DECL) { - if (!TYPE_P (TREE_TYPE (f))) + tree field_type = TREE_TYPE (f); + if (!TYPE_P (field_type)) break; - /* If there's vector_size attribute, ignore it. */ - if (VECTOR_TYPE_P (TREE_TYPE (f))) - is_vector = !riscv_arg_has_vector_size_attribute (type); + /* Ignore it if it's fixed length vector. */ + if (VECTOR_TYPE_P (field_type)) + is_vector = !riscv_scalable_vector_type_p (field_type); else - is_vector = riscv_arg_has_vector (TREE_TYPE (f)); + is_vector = riscv_arg_has_vector (field_type); } break; case VECTOR_TYPE: - is_vector = !riscv_arg_has_vector_size_attribute (type); + is_vector = !riscv_scalable_vector_type_p (type); break; default: From 33484c5db40af98b583ec5e0d6befa911b50845e Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Mon, 24 Apr 2023 16:24:51 +0800 Subject: [PATCH 6/7] fix: address comments. --- gcc/config/riscv/riscv.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6ff33abb75f..06e9fe7d924 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3736,10 +3736,10 @@ riscv_scalable_vector_type_p (const_tree type) { tree size = TYPE_SIZE (type); if (size && TREE_CODE (size) == INTEGER_CST) - return true; + return false; /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ - return false; + return true; } static bool @@ -3762,7 +3762,7 @@ riscv_arg_has_vector (const_tree type) /* Ignore it if it's fixed length vector. */ if (VECTOR_TYPE_P (field_type)) - is_vector = !riscv_scalable_vector_type_p (field_type); + is_vector = riscv_scalable_vector_type_p (field_type); else is_vector = riscv_arg_has_vector (field_type); } @@ -3770,7 +3770,7 @@ riscv_arg_has_vector (const_tree type) break; case VECTOR_TYPE: - is_vector = !riscv_scalable_vector_type_p (type); + is_vector = riscv_scalable_vector_type_p (type); break; default: @@ -3791,7 +3791,7 @@ riscv_pass_in_vector_p (const_tree type) if (type && riscv_arg_has_vector (type) && !warned) { - warning (OPT_Wpsabi, "ABI for the vector type is currently in " + warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in " "experimental stage and may changes in the upcoming version of " "GCC."); warned = 1; From a6c96b80b389c403944748c4578dc0987564f15b Mon Sep 17 00:00:00 2001 From: Yanzhang Wang Date: Mon, 22 May 2023 22:10:36 +0800 Subject: [PATCH 7/7] fix: disable intrinsic warning. --- gcc/config/riscv/riscv.cc | 42 ++++++++++++++++++++++++++++++++++++--- gcc/config/riscv/riscv.h | 6 +++++- 2 files changed, 44 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 06e9fe7d924..17f9753b9f4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3798,6 +3798,28 @@ riscv_pass_in_vector_p (const_tree type) } } +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +void +init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ + tree fntype, /* tree ptr for function decl */ + rtx libname, /* SYMBOL_REF of library name or 0 */ + tree fndecl, + int caller) +{ + memset (cum, 0, sizeof (*cum)); + + if (fndecl) + { + const tree_function_decl &fn = FUNCTION_DECL_CHECK (fndecl)->function_decl; + + if (fn.built_in_class == NOT_BUILT_IN) + cum->rvv_psabi_warning = 1; + } +} + /* Fill INFO with information about a single argument, and return an RTL pattern to pass or return the argument. CUM is the cumulative state for earlier arguments. MODE is the mode of this argument and @@ -3882,8 +3904,11 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, } } - /* Only check existing of vector type. */ - riscv_pass_in_vector_p (type); + if (cum->rvv_psabi_warning) + { + /* Only check existing of vector type. */ + riscv_pass_in_vector_p (type); + } /* Work out the size of the argument. */ num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant (); @@ -3972,7 +3997,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode) } memset (&args, 0, sizeof args); - return riscv_get_arg_info (&info, &args, mode, type, true, true); + + const_tree arg_type = type; + if (func && DECL_RESULT (func)) + { + const tree_function_decl &fn = FUNCTION_DECL_CHECK(func)->function_decl; + if (fn.built_in_class == NOT_BUILT_IN) + args.rvv_psabi_warning = 1; + + arg_type = TREE_TYPE (DECL_RESULT (func)); + } + + return riscv_get_arg_info (&info, &args, mode, arg_type, true, true); } /* Implement TARGET_PASS_BY_REFERENCE. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 66fb07d6652..051da8d1c15 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -671,14 +671,18 @@ typedef struct { /* Number of floating-point registers used so far, likewise. */ unsigned int num_fprs; + + bool rvv_psabi_warning; } CUMULATIVE_ARGS; /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ +void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ - memset (&(CUM), 0, sizeof (CUM)) + init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ + (N_NAMED_ARGS) != -1) #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)