TSC Meeting October 2021 - Call for Agenda

[lgirdwood]

TSC Meeting
@thesofproject/steering-committee Now that v1.9 is out let discuss the plans for v1.10 and discuss opens and agenda items.

**Date: Tuesday 19th October 4 - 5PM UK time **
Doodle: https://doodle.com/poll/5pvk77x9mmndb5am
Meeting will be 1 hour, but may take longer if topics require more discussion and alignment.

Agenda

1. v1.9 release review. Feedback into process, what are we doing right, wrong and how can we improve. The v1.9 cycle was 3 months total, with 2 months feature development and 1 month stabilization.
2. v1.10 release planning. Proposed features and release cadence. Rename to v2.0 ???
3. Windows integration plans and upcoming proposed changes (Liam/Michal).
4. Zephyr integration next steps (Liam/??).
5. Multicore updates (Liam). Object coherency, Heterogeneous multicore architectures (Bhiregoudar, possibly lead to a followup call).
6. Compress parameters (Daniel) https://github.com/orgs/thesofproject/teams/sof-developers/discussions/56
7. Switch from xcc to xt-clang compiler
8. Firmware and topology release dependency discussion about making FW and topology releases independent to each other
9. AOB

[marc-hb]

C99 declarations https://github.com/orgs/thesofproject/teams/steering-committee/discussions/25 tl;dr: can we officially allow a useful, 20 years old feature that we've already been using for years by "accident"?

[cujomalainey]

Can we get an update on converged module repo readiness?

[dbaluta]

@lgirdwood added doodle link. Please distribute this to Google and AMD guys. I think we should also invite Mediatek people but I'm afraid it will be hard for them to join because of the late time (they are based in Asia).

[lgirdwood]

@bhiregoudar @sunilkumardommati @yaochunhung @kuanhsuncheng not sure if you guys have seen this yet. Please suggest topics and use the doodle to let us know availability.

[bhiregoudar]

Thanks for the invitation, Would like to add few topics for discussion. 1. In case of multiple DSP case, if two different type of Xtensa DSP configurations are used? Then how the SOF supports this scenario. In this case, the firmware images of DSP's would be different and not shared across different DSP's. Even may be the case where one DSP would be Xtensa and one DSP would be ARM or some other DSP. Mechanism for building and loading of multiple firmware images to different DSP's in different memory blocks? 2. Separating the core firmware and components, means create different firmware image and component image 3. Supporting latest Xtensa toolchain

[plbossart]

1. In case of multiple DSP case, if two different type of Xtensa DSP configurations are used? Then how the SOF supports this scenario. In this case, the firmware images of DSP's would be different and not shared across different DSP's. Even may be the case where one DSP would be Xtensa and one DSP would be ARM or some other DSP.

The TSC meetings frequently go over time and this ask could take the entire meeting @bhiregoudar. As you can see above there's already quite a bit of work on-going to support symmetric multi-processing assuming ISA compatibility. Hererogeneous processing is something else, several orders of magnitude more complicated.

May I suggest that you prepare a one-page summary, shared ahead of the meeting, of the tentative configurations you'd like to see supported. Usually for this sort of configuration you have a primary DSP which controls the others, if not you would need quite a bit of driver code on the host. Currently the Linux driver will support a single firmware file and boot process.

Thanks!

[cujomalainey]

I think MTK would also be interested in 3. as well

[kuanhsuncheng]

Hi Liam,

Thanks for asking.

I have updated available time in Doodle.

[lgirdwood]

Looks like Tuesday 4-5pm UK time is possibly best. Will send invite out.