@SimulatableIntrinsic not treated as intrinsic for circuit diagram

[swernli]

A normal intrinsic like this:

will fail to run but show a circuit diagram as I expected. Meanwhile, a simulatable intrinsic like this:

will successfully simulate but shows the simulated gates in the diagram rather than the intrinsic.

I'm not sure if there is a reasonable way to fix this, as the point of simulatable intrinsics is to execute the body in simulation, and the backend chaining used for circuit diagrams is itself just simulation. On some level, this asks the question: is the circuit diagram meant to show what is run in simulation or to visualize what would be produced in QIR codegen? If the former, then this behavior is expected and not really a bug. If the latter, then we'd need to find a way to have the chaining backend differentiate between normal simulation and simulatable intrinsic, which the infrastructure doesn't really accommodate.