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1bitmemorycell.circ
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1bitmemorycell.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.8.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(110,190)" name="Pin">
<a name="appearance" val="classic"/>
<a name="label" val="WE"/>
</comp>
<comp lib="0" loc="(110,270)" name="Pin">
<a name="appearance" val="classic"/>
<a name="label" val="D"/>
</comp>
<comp lib="0" loc="(110,330)" name="Pin">
<a name="appearance" val="classic"/>
<a name="label" val="OE"/>
</comp>
<comp lib="0" loc="(110,370)" name="Clock">
<a name="label" val="CLK"/>
</comp>
<comp lib="0" loc="(110,410)" name="Pin">
<a name="appearance" val="classic"/>
<a name="label" val="RESET"/>
</comp>
<comp lib="1" loc="(190,190)" name="NOT Gate"/>
<comp lib="1" loc="(280,170)" name="AND Gate"/>
<comp lib="1" loc="(280,250)" name="AND Gate"/>
<comp lib="1" loc="(370,210)" name="OR Gate"/>
<comp lib="1" loc="(640,210)" name="Controlled Buffer"/>
<comp lib="4" loc="(450,200)" name="D Flip-Flop">
<a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="8" loc="(402,199)" name="Text">
<a name="text" val="temp_D"/>
</comp>
<comp lib="8" loc="(532,240)" name="Text">
<a name="text" val="QNOT"/>
</comp>
<comp lib="8" loc="(687,200)" name="Text">
<a name="text" val="DOUT"/>
</comp>
<wire from="(110,190)" to="(140,190)"/>
<wire from="(110,270)" to="(230,270)"/>
<wire from="(110,330)" to="(630,330)"/>
<wire from="(110,370)" to="(400,370)"/>
<wire from="(110,410)" to="(470,410)"/>
<wire from="(140,190)" to="(140,230)"/>
<wire from="(140,190)" to="(160,190)"/>
<wire from="(140,230)" to="(230,230)"/>
<wire from="(190,190)" to="(230,190)"/>
<wire from="(200,150)" to="(230,150)"/>
<wire from="(200,70)" to="(200,150)"/>
<wire from="(200,70)" to="(560,70)"/>
<wire from="(280,170)" to="(300,170)"/>
<wire from="(280,250)" to="(300,250)"/>
<wire from="(300,170)" to="(300,190)"/>
<wire from="(300,190)" to="(320,190)"/>
<wire from="(300,230)" to="(300,250)"/>
<wire from="(300,230)" to="(320,230)"/>
<wire from="(370,210)" to="(440,210)"/>
<wire from="(400,250)" to="(400,370)"/>
<wire from="(400,250)" to="(440,250)"/>
<wire from="(470,260)" to="(470,410)"/>
<wire from="(500,210)" to="(560,210)"/>
<wire from="(500,250)" to="(550,250)"/>
<wire from="(560,210)" to="(620,210)"/>
<wire from="(560,70)" to="(560,210)"/>
<wire from="(630,220)" to="(630,330)"/>
<wire from="(640,210)" to="(720,210)"/>
</circuit>
<vhdl name="dff">library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
CLK : in std_logic;
D : in std_logic;
RESET : in std_logic;
Q : out std_logic;
QNOT: out std_logic
);
end dff;
architecture behv of dff is
begin
process(CLK, RESET)
begin
if (RESET = '1') then
Q <= '0';
QNOT <= '1';
elsif rising_edge(CLK) then
Q <= D;
QNOT <= not D;
end if;
end process;
end behv;
</vhdl>
<vhdl name="tristate">library ieee;
use ieee.std_logic_1164.all;
entity tristate is
port (
A: in std_logic;
EN: in std_logic;
Y: out std_logic
);
end tristate;
architecture arch of tristate is
begin
tristate_process: process(A, EN)
begin
if (EN = '1') then
Y <= A;
else
Y <= 'Z'; -- Use 'Z' for tristate
end if;
end process tristate_process;
end arch;
</vhdl>
<vhdl name="memoryCell">library ieee;
use ieee.std_logic_1164.all;
entity memoryCell is
port (
CLK : in std_logic;
D : in std_logic;
RESET : in std_logic;
WE: in std_logic; -- write enable
OE: in std_logic; -- output enable
Q : out std_logic;
QNOT: out std_logic;
DOUT: out std_logic -- output of tristate buffer stage
) ;
end memoryCell ;
architecture mem of memoryCell is
signal temp_D: std_logic;
begin
temp_D <= ((not WE) and Q) or (WE and D);
dff_inst: dff
PORT(
CLK => CLK,
D => temp_D,
RESET => RESET,
Q => Q,
QNOT => QNOT
);
tri_inst: tristate
PORT(
A => Q,
EN => OE,
Y => DOUT
);
end mem;
</vhdl>
</project>