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STORM_SoC_basic_map.map
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STORM_SoC_basic_map.map
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Release 14.7 Map P.20131013 (lin64)
Xilinx Map Application Log File for Design 'STORM_SoC_basic'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx9-ftg256-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o STORM_SoC_basic_map.ncd STORM_SoC_basic.ngd
STORM_SoC_basic.pcf
Target Device : xc6slx9
Target Package : ftg256
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Feb 23 19:59:37 2015
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 13 secs
Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:6a5ada97) REAL time: 14 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 74 IOs, 66 are locked
and 8 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:6a5ada97) REAL time: 15 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:6a5ada97) REAL time: 15 secs
Phase 4.2 Initial Placement for Architecture Specific Features
....
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:6bb22577) REAL time: 22 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:6bb22577) REAL time: 22 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:6bb22577) REAL time: 22 secs
Phase 7.3 Local Placement Optimization
....
Phase 7.3 Local Placement Optimization (Checksum:6ce38c13) REAL time: 22 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:6ce38c13) REAL time: 22 secs
Phase 9.8 Global Placement
...........................
.....................................................................................................................................................
...........................................................................................................................................................................................
........................................................................................................................................
..................................................
Phase 9.8 Global Placement (Checksum:55ea1826) REAL time: 1 mins 18 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:55ea1826) REAL time: 1 mins 19 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:19ec1413) REAL time: 1 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:19ec1413) REAL time: 1 mins 34 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d3192dfb) REAL time: 1 mins 34 secs
Total REAL time to Placer completion: 1 mins 34 secs
Total CPU time to Placer completion: 1 mins 33 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE21_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE22_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE4_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE6_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE24_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE1_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE11_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE13_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE25_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE12_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE15_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE23_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE5_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 16
Slice Logic Utilization:
Number of Slice Registers: 3,886 out of 11,440 33%
Number used as Flip Flops: 3,885
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 1
Number of Slice LUTs: 5,275 out of 5,720 92%
Number used as logic: 5,157 out of 5,720 90%
Number using O6 output only: 4,285
Number using O5 output only: 253
Number using O5 and O6: 619
Number used as ROM: 0
Number used as Memory: 70 out of 1,440 4%
Number used as Dual Port RAM: 68
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 48
Number with same-slice register load: 11
Number with same-slice carry load: 37
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,426 out of 1,430 99%
Number of MUXCYs used: 824 out of 2,860 28%
Number of LUT Flip Flop pairs used: 5,531
Number with an unused Flip Flop: 1,822 out of 5,531 32%
Number with an unused LUT: 256 out of 5,531 4%
Number of fully used LUT-FF pairs: 3,453 out of 5,531 62%
Number of unique control sets: 130
Number of slice register sites lost
to control set restrictions: 341 out of 11,440 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 74 out of 186 39%
Number of LOCed IOBs: 66 out of 74 89%
IOB Flip Flops: 38
Specific Feature Utilization:
Number of RAMB16BWERs: 20 out of 32 62%
Number of RAMB8BWERs: 8 out of 64 12%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 16 out of 200 8%
Number used as ILOGIC2s: 16
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 16 out of 200 8%
Number used as IODELAY2s: 16
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 22 out of 200 11%
Number used as OLOGIC2s: 22
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 16 18%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.42
Peak Memory Usage: 801 MB
Total REAL time to MAP completion: 1 mins 39 secs
Total CPU time to MAP completion: 1 mins 38 secs
Mapping completed.
See MAP report file "STORM_SoC_basic_map.mrp" for details.