From 6af8c995a50e5eed3e86663ee1fffbcf79ff43ab Mon Sep 17 00:00:00 2001 From: Abhishek Anand Date: Mon, 12 Jun 2023 22:23:30 +0530 Subject: [PATCH 1/8] Initial experimental DSP support Signed-off-by: Abhishek Anand --- utils/lib/progressbar_utils.py | 2 +- .../common/primitives/dsp48e1/CMakeLists.txt | 37 +++-- .../primitives/dsp48e1/dsp48e1.model.xml | 57 +++++++ .../primitives/dsp48e1/dsp48e1.pb_type.xml | 72 ++++++++ xilinx/common/utils/.gdb_history | 2 + xilinx/common/utils/prjxray_arch_import.py | 3 + xilinx/common/utils/prjxray_db_cache.py | 3 +- .../utils/prjxray_physical_tile_import.py | 3 +- xilinx/common/utils/prjxray_routing_import.py | 14 +- xilinx/common/utils/prjxray_tile_import.py | 15 +- .../devices/xc7a50t-virt/CMakeLists.txt | 4 + xilinx/xc7/archs/artix7/tiles/CMakeLists.txt | 4 + .../archs/artix7/tiles/dsp48e1/CMakeLists.txt | 7 + .../archs/artix7/tiles/dsp_l/CMakeLists.txt | 5 + .../archs/artix7/tiles/dsp_r/CMakeLists.txt | 5 + .../archs/artix7/tiles/tieoff/CMakeLists.txt | 7 + xilinx/xc7/techmap/cells_map.v | 157 ++++++++++++++++++ xilinx/xc7/techmap/cells_sim.v | 70 ++++++++ xilinx/xc7/tests/CMakeLists.txt | 1 + xilinx/xc7/tests/dsp/CMakeLists.txt | 9 + xilinx/xc7/tests/dsp/dsp.xdc | 60 +++++++ xilinx/xc7/tests/dsp/top.v | 79 +++++++++ 22 files changed, 583 insertions(+), 33 deletions(-) create mode 100644 xilinx/common/primitives/dsp48e1/dsp48e1.model.xml create mode 100644 xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml create mode 100644 xilinx/common/utils/.gdb_history create mode 100644 xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt create mode 100644 xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt create mode 100644 xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt create mode 100644 xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt create mode 100644 xilinx/xc7/tests/dsp/CMakeLists.txt create mode 100644 xilinx/xc7/tests/dsp/dsp.xdc create mode 100644 xilinx/xc7/tests/dsp/top.v diff --git a/utils/lib/progressbar_utils.py b/utils/lib/progressbar_utils.py index 596dfae03f..ed4cbd8226 100644 --- a/utils/lib/progressbar_utils.py +++ b/utils/lib/progressbar_utils.py @@ -11,7 +11,7 @@ def disable_widgets_if_not_interactive(kwargs): def progressbar(*args, **kwargs): disable_widgets_if_not_interactive(kwargs) - b = bar.progressbar(*args, **kwargs) + b = bar.progressbar.ProgressBar(*args, **kwargs) return b diff --git a/xilinx/common/primitives/dsp48e1/CMakeLists.txt b/xilinx/common/primitives/dsp48e1/CMakeLists.txt index 4e58dff22d..25d4df8062 100644 --- a/xilinx/common/primitives/dsp48e1/CMakeLists.txt +++ b/xilinx/common/primitives/dsp48e1/CMakeLists.txt @@ -1,17 +1,20 @@ -add_subdirectory(nreg) -add_subdirectory(alu) -add_subdirectory(alumode_mux) -add_subdirectory(carryinsel_logic) -add_subdirectory(carryinsel_mux) -add_subdirectory(creg_mux) -add_subdirectory(dual_ad_preadder) -add_subdirectory(dual_b_reg) -add_subdirectory(inmode_mux) -add_subdirectory(mult25x18) -add_subdirectory(mult_mux) -add_subdirectory(opmode_mux) -add_subdirectory(xmux) -add_subdirectory(ymux) -add_subdirectory(zmux) -add_file_target(FILE dsp48e1.sim.v SCANNER_TYPE verilog) -v2x(NAME dsp48e1 SRCS dsp48e1.sim.v) +#add_subdirectory(nreg) +#add_subdirectory(alu) +#add_subdirectory(alumode_mux) +#add_subdirectory(carryinsel_logic) +#add_subdirectory(carryinsel_mux) +#add_subdirectory(creg_mux) +#add_subdirectory(dual_ad_preadder) +#add_subdirectory(dual_b_reg) +#add_subdirectory(inmode_mux) +#add_subdirectory(mult25x18) +#add_subdirectory(mult_mux) +#add_subdirectory(opmode_mux) +#add_subdirectory(xmux) +#add_subdirectory(ymux) +#add_subdirectory(zmux) +#add_file_target(FILE dsp48e1.sim.v SCANNER_TYPE verilog) +#v2x(NAME dsp48e1 SRCS dsp48e1.sim.v) + +add_file_target(FILE dsp48e1.model.xml SCANNER_TYPE xml) +add_file_target(FILE dsp48e1.pb_type.xml SCANNER_TYPE xml) diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml new file mode 100644 index 0000000000..8754ce53a4 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml new file mode 100644 index 0000000000..8c8ec7d060 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +AREG_0=AREG_0 +BREG_0=BREG_0 +MASK[47:0]=MASK +ZADREG[0]=ADREG +ZALUMODEREG[0]=ALUMODEREG +ZAREG_2_ACASCREG_1=ACASCREG +ZBREG_2_BCASCREG_1=BCASCREG +ZCARRAYINREG[0]=CARRAYINREG +ZCARRYINSELREG[0]=CARRYINSELREG +ZDREG[0]=DREG +ZINMODEREG[0]=INMODEREG +ZMREG[0]=MREG +ZOPMODEREG[0]=OPMODEREG +ZPREG[0]=PREG +ZIS_ALUMODE_INVERTED[3:0]=IS_ALUMODE_INVERTED +ZIS_INMODE_INVERTED[4:0]=IS_INMODE_INVERTED +ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED + + + diff --git a/xilinx/common/utils/.gdb_history b/xilinx/common/utils/.gdb_history new file mode 100644 index 0000000000..0e6970a866 --- /dev/null +++ b/xilinx/common/utils/.gdb_history @@ -0,0 +1,2 @@ +exit() +file prjxray_tile_import.py diff --git a/xilinx/common/utils/prjxray_arch_import.py b/xilinx/common/utils/prjxray_arch_import.py index 3a41f3e9cf..c3a301c47c 100644 --- a/xilinx/common/utils/prjxray_arch_import.py +++ b/xilinx/common/utils/prjxray_arch_import.py @@ -521,11 +521,14 @@ def is_in_roi(conn, roi, tile_pkey): "IBUFDS_GTE2": ("Y", 2), "IPAD": (None, None), "OPAD": (None, None), + "DSP48E1": ("X", 2), + "TIEOFF": (None, None) } def make_prefix(site, x, y, from_site_name=False): """ Make tile FASM prefix for a given site. """ + if from_site_name: site_type, _ = site.split('_') else: diff --git a/xilinx/common/utils/prjxray_db_cache.py b/xilinx/common/utils/prjxray_db_cache.py index 5d916f8df5..57d330eabb 100644 --- a/xilinx/common/utils/prjxray_db_cache.py +++ b/xilinx/common/utils/prjxray_db_cache.py @@ -73,6 +73,7 @@ def _progress(self, status, remaining, total): Prints database copy progress. """ if self.bar is None: - self.bar = ProgressBar(max_value=total) + self.bar = ProgressBar(maxval=total) + self.bar.start() else: self.bar.update(total - remaining) diff --git a/xilinx/common/utils/prjxray_physical_tile_import.py b/xilinx/common/utils/prjxray_physical_tile_import.py index ca53435f41..6ad2c60867 100755 --- a/xilinx/common/utils/prjxray_physical_tile_import.py +++ b/xilinx/common/utils/prjxray_physical_tile_import.py @@ -78,7 +78,8 @@ def add_direct_mappings(tile_xml, site_xml, eq_pb_type_xml): def add_equivalent_sites(tile_xml, equivalent_sites): """ Used to add to the tag the equivalent tiles associated with it.""" - + if equivalent_sites=="": + return pb_types = equivalent_sites.split(',') equivalent_sites_xml = ET.SubElement(tile_xml, 'equivalent_sites') diff --git a/xilinx/common/utils/prjxray_routing_import.py b/xilinx/common/utils/prjxray_routing_import.py index 4e9560d3f8..69f43584d3 100755 --- a/xilinx/common/utils/prjxray_routing_import.py +++ b/xilinx/common/utils/prjxray_routing_import.py @@ -684,7 +684,7 @@ def import_tracks(conn, alive_tracks, node_mapping, graph, default_segment_id): cur2 = conn.cursor() for (graph_node_pkey, track_pkey, graph_node_type, x_low, x_high, y_low, y_high, ptc, capacitance, - resistance) in progressbar_utils.progressbar(cur.execute(""" + resistance) in cur.execute(""" SELECT pkey, track_pkey, @@ -697,7 +697,7 @@ def import_tracks(conn, alive_tracks, node_mapping, graph, default_segment_id): capacitance, resistance FROM - graph_node WHERE track_pkey IS NOT NULL;""")): + graph_node WHERE track_pkey IS NOT NULL;"""): if track_pkey not in alive_tracks: continue @@ -997,8 +997,7 @@ def import_graph_edges(conn, graph, extra_features, node_mapping): nodes_set = set() print('{} Importing edges from database.'.format(now())) - with progressbar_utils.ProgressBar(max_value=num_edges) as bar: - for idx, (src_graph_node, dest_graph_node, switch_pkey, phy_tile_pkey, + for idx, (src_graph_node, dest_graph_node, switch_pkey, phy_tile_pkey, pip_pkey, backward) in enumerate(cur.execute(""" SELECT src_graph_node_pkey, @@ -1096,8 +1095,7 @@ def create_channels(conn): def yield_nodes(nodes): - with progressbar_utils.ProgressBar(max_value=len(nodes)) as bar: - for idx, node in enumerate(nodes): + for idx, node in enumerate(nodes): yield node if idx % 1024 == 0: @@ -1318,8 +1316,8 @@ def main(): args.vpr_capnp_schema_dir, 'rr_graph_uxsdcxx.capnp' ), input_file_name=args.read_rr_graph, - progressbar=progressbar_utils.progressbar, - output_file_name=args.write_rr_graph, + + output_file_name=args.write_rr_graph ) graph = capnp_graph.graph diff --git a/xilinx/common/utils/prjxray_tile_import.py b/xilinx/common/utils/prjxray_tile_import.py index 36407bd64e..5f81ad5168 100755 --- a/xilinx/common/utils/prjxray_tile_import.py +++ b/xilinx/common/utils/prjxray_tile_import.py @@ -332,10 +332,12 @@ def x_filter_func(site): if site.type not in site_type_count: site_type_count[site.type] = 0 site_prefixes[site.type] = [] - + cells_idx[idx] = site_type_count[site.type] site_type_count[site.type] += 1 - + + '''print(cells_idx[idx]," ",site_type_count[site.type]," ",site.type)''' + site_coords = args.site_coords.upper() if site_coords == 'X': site_prefix = '{}_X{}'.format(site.type, site.x) @@ -352,6 +354,8 @@ def x_filter_func(site): site_instance = site_type_instances[site.type][cells_idx[idx]] idx += 1 + + '''print(site_instance)''' if (site.type, site_instance) not in models_added: models_added.add((site.type, site_instance)) @@ -374,11 +378,12 @@ def x_filter_func(site): for outputs in root_element.iter('output'): ports[outputs.attrib['name']] = int(outputs.attrib['num_pins']) - assert site_instance not in site_type_ports, ( + '''assert site_instance not in site_type_ports, ( site_instance, site_type_ports.keys() ) + print(site_instance)''' site_type_ports[site_instance] = ports - + attrib = dict(root_element.attrib) include_xml = ET.SubElement(pb_type_xml, 'pb_type', attrib) ET.SubElement( @@ -1393,7 +1398,7 @@ def main(): parser.add_argument('--tile', help="""Tile to generate for""") parser.add_argument( - '--site_directory', help="""Diretory where sites are defined""" + '--site_directory', help="""Directory where sites are defined""" ) parser.add_argument( diff --git a/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt b/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt index 3848af91c6..ad6053979e 100644 --- a/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt +++ b/xilinx/xc7/archs/artix7/devices/xc7a50t-virt/CMakeLists.txt @@ -26,6 +26,8 @@ add_xc_device_define_type( GTP_CHANNEL_2 GTP_CHANNEL_3 PCIE_BOT + DSP_L + DSP_R PB_TYPES SLICEL SLICEM @@ -43,4 +45,6 @@ add_xc_device_define_type( IPAD OPAD PCIE_2_1 + DSP48E1 + TIEOFF ) diff --git a/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt index b258dc9594..fa312d98cd 100644 --- a/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt +++ b/xilinx/xc7/archs/artix7/tiles/CMakeLists.txt @@ -25,6 +25,10 @@ add_subdirectory(pcie_bot) add_subdirectory(mmcme2_adv) add_subdirectory(cmt_top_l_lower_b) add_subdirectory(cmt_top_r_lower_b) +add_subdirectory(dsp_l) +add_subdirectory(dsp_r) +add_subdirectory(dsp48e1) +add_subdirectory(tieoff) set(IOPAD_SITES IOB33 IDELAYE2 ILOGICE3 OLOGICE3) set(IOPAD_S_SITES IOB33S IDELAYE2 ILOGICE3 OLOGICE3) diff --git a/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt new file mode 100644 index 0000000000..39cb5a9f54 --- /dev/null +++ b/xilinx/xc7/archs/artix7/tiles/dsp48e1/CMakeLists.txt @@ -0,0 +1,7 @@ +project_ray_tile( + ARCH artix7 + TILE DSP48E1 + SITE_AS_TILE + SITE_TYPES DSP48E1/DSP48E1 + EQUIVALENT_SITES DSP48E1 + ) diff --git a/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt new file mode 100644 index 0000000000..b6522ed01f --- /dev/null +++ b/xilinx/xc7/archs/artix7/tiles/dsp_l/CMakeLists.txt @@ -0,0 +1,5 @@ +project_ray_tile_capacity( + ARCH artix7 + TILE DSP_L + SITE_TYPES DSP48E1/DSP48E1 DSP48E1/DSP48E1 TIEOFF/TIEOFF + ) diff --git a/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt new file mode 100644 index 0000000000..31f260040b --- /dev/null +++ b/xilinx/xc7/archs/artix7/tiles/dsp_r/CMakeLists.txt @@ -0,0 +1,5 @@ +project_ray_tile_capacity( + ARCH artix7 + TILE DSP_R + SITE_TYPES DSP48E1/DSP48E1 DSP48E1/DSP48E1 TIEOFF/TIEOFF + ) diff --git a/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt b/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt new file mode 100644 index 0000000000..7361df52de --- /dev/null +++ b/xilinx/xc7/archs/artix7/tiles/tieoff/CMakeLists.txt @@ -0,0 +1,7 @@ +project_ray_tile( + ARCH artix7 + TILE TIEOFF + SITE_AS_TILE + SITE_TYPES TIEOFF/TIEOFF + EQUIVALENT_SITES TIEOFF + ) diff --git a/xilinx/xc7/techmap/cells_map.v b/xilinx/xc7/techmap/cells_map.v index 4cc339a149..f1d74c9f67 100644 --- a/xilinx/xc7/techmap/cells_map.v +++ b/xilinx/xc7/techmap/cells_map.v @@ -10793,3 +10793,160 @@ module PCIE_2_1 ( .USERRSTN(USERRSTN) ); endmodule + + +module DSP48E1 ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output reg PATTERNBDETECT, + output reg PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + (* clkbuf_sink *) input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + + DSP48E1_VPR #( + + .AREG_0(AREG==0), + .BREG(BREG==0), + .MASK(MASK), + .ADREG(ADREG[0]), + .ALUMODEREG(ALUMODEREG[0]), + .ACASCREG(ACASCREG[0]), + .BCASCREG(BCASCREG[0]), + .CARRYINREG(CARRYINREG[0]), + .CARRYINSELREG(CARRYINSELREG[0]), + .DREG(DREG[0]), + .INMODEREG(INMODEREG[0]), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_INMODE_INVERTED(IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED), + .MREG(MREG[0]), + .OPMODEREG(OPMODEREG[0]), + .PREG(PREG[0]) + + ) _TECHMAP_REPLACE_ ( + .ACOUT(ACOUT), + .BCOUT(BCOUT), + .CARRYCASCOUT(CARRYCASCOUT), + .CARRYOUT(CARRYOUT), + .MULTSIGNOUT(MULTSIGNOUT), + .OVERFLOW(OVERFLOW), + .P(P), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT(PATTERNDETECT), + .PCOUT(PCOUT), + .UNDERFLOW(UNDERFLOW), + .A(A), + .ACIN(ACIN), + .ALUMODE(ALUMODE), + .B(B), + .BCIN(BCIN), + .C(C), + .CARRYCASIN(CARRYCASCIN), + .CARRYIN(CARRYIN), + .CARRYINSEL(CARRYINSEL), + .CEA1(CEA1), + .CEA2(CEA2), + .CEAD(CEAD), + .CEALUMODE(CEALUMODE), + .CEB1(CEB1), + .CEB2(CEB2), + .CEC(CEC), + .CECARRYIN(CECARRYIN), + .CECTRL(CECTRL), + .CED(CED), + .CEINMODE(CEINMODE), + .CEM(CEM), + .CEP(CEP), + .CLK(CLK), + .D(D), + .INMODE(INMODE), + .MULTSIGNIN(MULTSIGNIN), + .OPMODE(OPMODE), + .PCIN(PCIN), + .RSTA(RSTA), + .RSTALLCARRYIN(RSTALLCARRYIN), + .RSTALUMODE(RSTALUMODE), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTCTRL(RSTCTRL), + .RSTD(RSTD), + .RSTINMODE(RSTINMODE), + .RSTM(RSTM), + .RSTP(RSTP) + ); + +endmodule diff --git a/xilinx/xc7/techmap/cells_sim.v b/xilinx/xc7/techmap/cells_sim.v index a06ebbe5e8..60ca8d71da 100644 --- a/xilinx/xc7/techmap/cells_sim.v +++ b/xilinx/xc7/techmap/cells_sim.v @@ -3575,3 +3575,73 @@ module PCIE_2_1_VPR ( parameter [4:0] VC0_TX_LASTPACKET = 5'd0; parameter [1:0] CFG_ECRC_ERR_CPLSTAT = 2'd0; endmodule + +module DSP48E1_VPR ( + input [29:0] A, + input [17:0] B, + input [47:0] C, + input [24:0] D, + input [6:0] OPMODE, + input [3:0] ALUMODE, + input CARRYIN, + input [2:0] CARRYINSEL, + input [4:0] INMODE, + input CEA1, + input CEA2, + input CEB1, + input CEB2, + input CEC, + input CED, + input CEM, + input CEP, + input CEAD, + input CEALUMODE, + input CECTRL, + input CECARRYIN, + input CEINMODE, + input RSTA, + input RSTB, + input RSTC, + input RSTD, + input RSTM, + input RSTP, + input RSTCTRL, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTINMODE, + input CLK, + input [29:0] ACIN, + input [17:0] BCIN, + input [47:0] PCIN, + input CARRYCASCIN, + input MULTSIGNIN, + output [29:0] ACOUT, + output [17:0] BCOUT, + output [47:0] PCOUT, + output [47:0] P, + output [3:0] CARRYOUT, + output CARRYCASCOUT, + output MULTSIGNOUT, + output PATTERNDETECT, + output PATTERNBDETECT, + output OVERFLOW, + output UNDERFLOW, +); + parameter AREG_0 = 1'b0; + parameter BREG_0 = 1'b0; + parameter MASK = 46'b0000000000000000000000000000000000000000000000; + parameter ADREG = 1'b0; + parameter ALUMODEREG = 1'b0; + parameter ACASCREG = 1'b0; + parameter BCASCREG = 1'b0; + parameter CARRYINREG = 1'b0; + parameter CARRYINSELREG = 1'b0; + parameter DREG = 1'b0; + parameter INMODEREG = 1'b0; + parameter MREG = 1'b0; + parameter OPMODEREG = 1'b0; + parameter PREG = 1'b0; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +endmodule diff --git a/xilinx/xc7/tests/CMakeLists.txt b/xilinx/xc7/tests/CMakeLists.txt index 4408f5ae44..244d6f1070 100644 --- a/xilinx/xc7/tests/CMakeLists.txt +++ b/xilinx/xc7/tests/CMakeLists.txt @@ -45,6 +45,7 @@ add_subdirectory(gtp_common) add_subdirectory(gtp_channel) add_subdirectory(pcie) add_subdirectory(pcie_complex) +add_subdirectory(dsp) # Tests with dependencies set(COUNTER_SRC ${f4pga-arch-defs_SOURCE_DIR}/xilinx/xc7/tests/counter) diff --git a/xilinx/xc7/tests/dsp/CMakeLists.txt b/xilinx/xc7/tests/dsp/CMakeLists.txt new file mode 100644 index 0000000000..527b4dc11b --- /dev/null +++ b/xilinx/xc7/tests/dsp/CMakeLists.txt @@ -0,0 +1,9 @@ +add_file_target(FILE dsp.xdc) +add_file_target(FILE top.v SCANNER_TYPE verilog) +add_fpga_target( + NAME dsp + BOARD arty-full + SOURCES top.v + INPUT_XDC_FILES dsp.xdc + EXPLICIT_ADD_FILE_TARGET +) diff --git a/xilinx/xc7/tests/dsp/dsp.xdc b/xilinx/xc7/tests/dsp/dsp.xdc new file mode 100644 index 0000000000..e9cae4acbb --- /dev/null +++ b/xilinx/xc7/tests/dsp/dsp.xdc @@ -0,0 +1,60 @@ +set_property PACKAGE_PIN G16 [get_ports {A[23]}] +set_property PACKAGE_PIN C17 [get_ports {A[9]}] +set_property PACKAGE_PIN J17 [get_ports {A[4]}] +set_property PACKAGE_PIN A15 [get_ports {B[9]}] +set_property PACKAGE_PIN U14 [get_ports {OUT[6]}] +set_property PACKAGE_PIN H17 [get_ports {A[14]}] +set_property PACKAGE_PIN J15 [get_ports {A[1]}] +set_property PACKAGE_PIN A14 [get_ports {B[6]}] +set_property PACKAGE_PIN U13 [get_ports {OUT[3]}] +set_property PACKAGE_PIN C16 [get_ports {A[10]}] +set_property PACKAGE_PIN U11 [get_ports {OUT[11]}] +set_property PACKAGE_PIN J13 [get_ports {A[15]}] +set_property PACKAGE_PIN E18 [get_ports {A[8]}] +set_property PACKAGE_PIN U17 [get_ports {OUT[16]}] +set_property PACKAGE_PIN R10 [get_ports {OUT[0]}] +set_property PACKAGE_PIN E17 [get_ports {A[18]}] +set_property PACKAGE_PIN K15 [get_ports {A[2]}] +set_property PACKAGE_PIN D15 [get_ports {B[1]}] +set_property PACKAGE_PIN V12 [get_ports {OUT[9]}] +set_property PACKAGE_PIN F15 [get_ports {A[22]}] +set_property PACKAGE_PIN H14 [get_ports {A[20]}] +set_property PACKAGE_PIN H15 [get_ports {A[11]}] +set_property PACKAGE_PIN A18 [get_ports {B[4]}] +set_property PACKAGE_PIN E15 [get_ports {B[3]}] +set_property PACKAGE_PIN T10 [get_ports {OUT[1]}] +set_property PACKAGE_PIN F14 [get_ports {B[14]}] +set_property PACKAGE_PIN D13 [get_ports {B[12]}] +set_property PACKAGE_PIN E16 [get_ports {B[2]}] +set_property PACKAGE_PIN F16 [get_ports {A[21]}] +set_property PACKAGE_PIN G17 [get_ports {A[13]}] +set_property PACKAGE_PIN B18 [get_ports {B[5]}] +set_property PACKAGE_PIN C15 [get_ports {B[0]}] +set_property PACKAGE_PIN B11 [get_ports {B[17]}] +set_property PACKAGE_PIN V10 [get_ports {OUT[8]}] +set_property PACKAGE_PIN K13 [get_ports {A[16]}] +set_property PACKAGE_PIN D18 [get_ports {A[7]}] +set_property PACKAGE_PIN B16 [get_ports {B[11]}] +set_property PACKAGE_PIN V17 [get_ports {OUT[13]}] +set_property PACKAGE_PIN V11 [get_ports {OUT[7]}] +set_property PACKAGE_PIN J14 [get_ports {A[12]}] +set_property PACKAGE_PIN K16 [get_ports {A[0]}] +set_property PACKAGE_PIN F13 [get_ports {B[15]}] +set_property PACKAGE_PIN T11 [get_ports {OUT[12]}] +set_property PACKAGE_PIN D12 [get_ports {B[13]}] +set_property PACKAGE_PIN G18 [get_ports {A[6]}] +set_property PACKAGE_PIN U18 [get_ports {OUT[15]}] +set_property PACKAGE_PIN G14 [get_ports {A[19]}] +set_property PACKAGE_PIN D17 [get_ports {A[17]}] +set_property PACKAGE_PIN B17 [get_ports {B[10]}] +set_property PACKAGE_PIN A16 [get_ports {B[8]}] +set_property PACKAGE_PIN A13 [get_ports {B[7]}] +set_property PACKAGE_PIN U16 [get_ports {OUT[14]}] +set_property PACKAGE_PIN H16 [get_ports {A[24]}] +set_property PACKAGE_PIN U12 [get_ports {OUT[10]}] +set_property PACKAGE_PIN F18 [get_ports {A[5]}] +set_property PACKAGE_PIN V14 [get_ports {OUT[5]}] +set_property PACKAGE_PIN T13 [get_ports {OUT[4]}] +set_property PACKAGE_PIN A11 [get_ports {B[16]}] +set_property PACKAGE_PIN T9 [get_ports {OUT[2]}] +set_property PACKAGE_PIN J18 [get_ports {A[3]}] diff --git a/xilinx/xc7/tests/dsp/top.v b/xilinx/xc7/tests/dsp/top.v new file mode 100644 index 0000000000..7ad8dc78e8 --- /dev/null +++ b/xilinx/xc7/tests/dsp/top.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps + +module top + ( + A, + B, + OUT + ); + + + (* IOSTANDARD = "LVCMOS33" *) input wire [24:0] A; + (* IOSTANDARD = "LVCMOS33" *) input wire [17:0] B; + (* IOSTANDARD = "LVCMOS33" *) output wire [16:0] OUT; + + + DSP48E1 #( + .AREG(1'b0), + .BREG(1'b0), + .MASK(48'b111111111111111111111111111111111111111111111111), + /* .ADREG(), + .ALUMODEREG(), + .ACASCREG(), + .BCASCREG(), + .CARRYINREG(), + .CARRYINSELREG(), + .DREG(), + .INMODEREG(), */ + .IS_ALUMODE_INVERTED(4'b1100), + .IS_INMODE_INVERTED(5'b11111), + .IS_OPMODE_INVERTED(7'b1000101), + /* .MREG(), + .OPMODEREG(), + .PREG() */ + ) + dsp25x18( + .A(A), + .ACIN(30'b000000000000000000000000000000), + .ALUMODE(4'b0011), + .B(B), + .BCIN(18'b000000000000000000), + .C(48'b111111111111111111111111111111111111111111111111), + .CARRYCASCIN(1'b0), + .CARRYIN(1'b0), + .CARRYINSEL(3'b000), + .CEA1(1'b0), + .CEA2(1'b0), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(1'b0), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(1'b0), + .CEP(1'b0), + .CLK(1'b0), + .D(25'b0000000000000000000000000), + .INMODE(5'b00000), + .MULTSIGNIN(1'b0), + .OPMODE(7'b0111111), + .PCIN(48'b000000000000000000000000000000000000000000000000), + .RSTA(1'b0), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(1'b0), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(1'b0), + .RSTP(1'b0), + .P(OUT) + ); + + + +endmodule // MULT25X18 From 02daac63bfc5205e88b3b8f8a66c9688ca798ba7 Mon Sep 17 00:00:00 2001 From: Abhishek Anand Date: Mon, 12 Jun 2023 23:58:37 +0530 Subject: [PATCH 2/8] Experimental support for DSP Signed-off-by: Abhishek Anand --- utils/lib/progressbar_utils.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/utils/lib/progressbar_utils.py b/utils/lib/progressbar_utils.py index ed4cbd8226..596dfae03f 100644 --- a/utils/lib/progressbar_utils.py +++ b/utils/lib/progressbar_utils.py @@ -11,7 +11,7 @@ def disable_widgets_if_not_interactive(kwargs): def progressbar(*args, **kwargs): disable_widgets_if_not_interactive(kwargs) - b = bar.progressbar.ProgressBar(*args, **kwargs) + b = bar.progressbar(*args, **kwargs) return b From 6c2488793e554fefe2112bb8f346909260349985 Mon Sep 17 00:00:00 2001 From: Abhishek Anand Date: Tue, 27 Jun 2023 13:02:26 +0530 Subject: [PATCH 3/8] dsp48e1 architecture xml Signed-off-by: Abhishek Anand --- .../primitives/dsp48e1/dsp48e1.model.xml | 5 - .../primitives/dsp48e1/dsp48e1.pb_type.xml | 38 +- .../dual_ad_preadder/a1reg/a1reg.pb_type.xml | 730 ++++++++++++++++++ .../dual_ad_preadder/a1reg/reg.pb_type.xml | 9 + .../a1reg_mux/a1reg_mux.pb_type.xml | 18 + .../dual_ad_preadder/a2reg/a2reg.pb_type.xml | 730 ++++++++++++++++++ .../dual_ad_preadder/a2reg/reg.pb_type.xml | 9 + .../a2reg_mux/a2reg_mux.pb_type.xml | 18 + .../dual_ad_preadder/adreg/adreg.pb_type.xml | 610 +++++++++++++++ .../dsp48e1/dual_ad_preadder/adreg/nreg.sim.v | 23 + .../dual_ad_preadder/adreg/reg.pb_type.xml | 9 + .../dsp48e1/dual_ad_preadder/adreg/reg.sim.v | 20 + .../adreg_mux/adreg_mux.pb_type.xml | 18 + .../ain_mux/ain_mux.pb_type.xml | 18 + .../amult_mux/amult_mux.pb_type.xml | 18 + .../{acout_mux => aout_mux}/CMakeLists.txt | 0 .../aout_mux/acout_mux.pb_type.xml | 18 + .../dual_ad_preadder/dreg/dreg.pb_type.xml | 610 +++++++++++++++ .../dsp48e1/dual_ad_preadder/dreg/nreg.sim.v | 23 + .../dual_ad_preadder/dreg/reg.pb_type.xml | 9 + .../dsp48e1/dual_ad_preadder/dreg/reg.sim.v | 20 + .../dreg_mux/dreg_mux.pb_type.xml | 18 + .../dual_ad_preadder.pb_type.xml | 38 + .../dual_b_reg/b1reg/b1reg.pb_type.xml | 442 +++++++++++ .../dsp48e1/dual_b_reg/b1reg/reg.pb_type.xml | 9 + .../b1reg_mux/b1reg_mux.pb_type.xml | 22 + .../dual_b_reg/b2reg/b1reg.pb_type.xml | 442 +++++++++++ .../dsp48e1/dual_b_reg/b2reg/reg.pb_type.xml | 9 + .../b2reg_mux/b2reg_mux.pb_type.xml | 22 + .../dual_b_reg/bin_mux/bin_mux.pb_type.xml | 22 + .../bmult_mux/bmult_mux.pb_type.xml | 19 + .../{bc_mux => bout_mux}/CMakeLists.txt | 0 .../dual_b_reg/bout_mux/bout_mux.pb_type.xml | 18 + .../dsp48e1/dual_b_reg/dual_b_reg.pb_type.xml | 14 + xilinx/common/utils/prjxray_arch_import.py | 2 +- xilinx/common/utils/prjxray_routing_import.py | 14 +- xilinx/xc7/techmap/cells_map.v | 12 +- xilinx/xc7/techmap/cells_sim.v | 4 +- 38 files changed, 4034 insertions(+), 26 deletions(-) create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/a1reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg_mux/a1reg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/a2reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg_mux/a2reg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/adreg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/nreg.sim.v create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/reg.sim.v create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg_mux/adreg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/ain_mux/ain_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/amult_mux/amult_mux.pb_type.xml rename xilinx/common/primitives/dsp48e1/dual_ad_preadder/{acout_mux => aout_mux}/CMakeLists.txt (100%) create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/acout_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/dreg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/nreg.sim.v create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/reg.sim.v create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg_mux/dreg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_ad_preadder/dual_ad_preadder.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/b1reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg_mux/b1reg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/b1reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/reg.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg_mux/b2reg_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/bin_mux/bin_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/bmult_mux/bmult_mux.pb_type.xml rename xilinx/common/primitives/dsp48e1/dual_b_reg/{bc_mux => bout_mux}/CMakeLists.txt (100%) create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/bout_mux.pb_type.xml create mode 100644 xilinx/common/primitives/dsp48e1/dual_b_reg/dual_b_reg.pb_type.xml diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml index 8754ce53a4..4df1a895c2 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml @@ -34,11 +34,6 @@ - - - - - diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml index 8c8ec7d060..9333cdf932 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml @@ -1,4 +1,4 @@ - + @@ -32,11 +32,6 @@ - - - - - @@ -48,6 +43,28 @@ + + + + + + + + + + + + + + + + + + + + + + AREG_0=AREG_0 @@ -70,3 +87,12 @@ ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED + + + + + +block +ignore + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/a1reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/a1reg.pb_type.xml new file mode 100644 index 0000000000..1122ce80cb --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/a1reg.pb_type.xml @@ -0,0 +1,730 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/reg.pb_type.xml new file mode 100644 index 0000000000..8118dafdfd --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg/reg.pb_type.xml @@ -0,0 +1,9 @@ + + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg_mux/a1reg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg_mux/a1reg_mux.pb_type.xml new file mode 100644 index 0000000000..1e6c2ad513 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a1reg_mux/a1reg_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +A1REG_MUX.BYPASS = A1REG_MUX.BYPASS +A1REG_MUX.REG = A1REG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/a2reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/a2reg.pb_type.xml new file mode 100644 index 0000000000..1122ce80cb --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/a2reg.pb_type.xml @@ -0,0 +1,730 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/reg.pb_type.xml new file mode 100644 index 0000000000..8118dafdfd --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg/reg.pb_type.xml @@ -0,0 +1,9 @@ + + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg_mux/a2reg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg_mux/a2reg_mux.pb_type.xml new file mode 100644 index 0000000000..a99e9cc307 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/a2reg_mux/a2reg_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +A2REG_MUX.BYPASS = A2REG_MUX.BYPASS +A2REG_MUX.REG = A2REG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/adreg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/adreg.pb_type.xml new file mode 100644 index 0000000000..719b341a08 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/adreg.pb_type.xml @@ -0,0 +1,610 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/nreg.sim.v b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/nreg.sim.v new file mode 100644 index 0000000000..8d79ceaa3f --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/nreg.sim.v @@ -0,0 +1,23 @@ +`ifndef DSP48_NREG_NREG +`define DSP48_NREG_NREG + +`include "reg.sim.v" + +module NREG(D, Q, CLK, CE, RESET); + parameter NBITS = 25; + + input wire [NBITS-1:0] D; + output reg [NBITS-1:0] Q; + input wire CLK; + input wire CE; + input wire RESET; + + genvar ii; + + for (ii=0; ii + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/reg.sim.v b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/reg.sim.v new file mode 100644 index 0000000000..608df8a59e --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg/reg.sim.v @@ -0,0 +1,20 @@ +`ifndef DSP48_NREG_REG +`define DSP48_NREG_REG + +module REG (D, Q, CLK, CE, RESET); + input wire D; + input wire CLK; + input wire CE; + input wire RESET; + output reg Q; + + always @(posedge CLK) begin + if (~RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end + +endmodule // REG + +`endif // `ifndef DSP48_NREG_REG diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg_mux/adreg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg_mux/adreg_mux.pb_type.xml new file mode 100644 index 0000000000..a0f862d80d --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/adreg_mux/adreg_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +ADREG_MUX.BYPASS = ADREG_MUX.BYPASS +ADREG_MUX.REG = ADREG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/ain_mux/ain_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/ain_mux/ain_mux.pb_type.xml new file mode 100644 index 0000000000..62c598a245 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/ain_mux/ain_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +AIN_MUX.A = AIN_MUX.A +AIN_MUX.ACIN = AIN_MUX.ACIN + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/amult_mux/amult_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/amult_mux/amult_mux.pb_type.xml new file mode 100644 index 0000000000..bd383036ee --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/amult_mux/amult_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +AMULT_MUX.A = AMULT_MUX.A +AMULT_MUX.ADDER_OUT = AMULT_MUX.ADDER_OUT + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/acout_mux/CMakeLists.txt b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/CMakeLists.txt similarity index 100% rename from xilinx/common/primitives/dsp48e1/dual_ad_preadder/acout_mux/CMakeLists.txt rename to xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/CMakeLists.txt diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/acout_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/acout_mux.pb_type.xml new file mode 100644 index 0000000000..58b90b07f9 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/aout_mux/acout_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +AOUT_MUX.I0 = AOUT_MUX.I0 +AOUT_MUX.I1 = AOUT_MUX.I1 + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/dreg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/dreg.pb_type.xml new file mode 100644 index 0000000000..719b341a08 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/dreg.pb_type.xml @@ -0,0 +1,610 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/nreg.sim.v b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/nreg.sim.v new file mode 100644 index 0000000000..8d79ceaa3f --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/nreg.sim.v @@ -0,0 +1,23 @@ +`ifndef DSP48_NREG_NREG +`define DSP48_NREG_NREG + +`include "reg.sim.v" + +module NREG(D, Q, CLK, CE, RESET); + parameter NBITS = 25; + + input wire [NBITS-1:0] D; + output reg [NBITS-1:0] Q; + input wire CLK; + input wire CE; + input wire RESET; + + genvar ii; + + for (ii=0; ii + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/reg.sim.v b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/reg.sim.v new file mode 100644 index 0000000000..608df8a59e --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg/reg.sim.v @@ -0,0 +1,20 @@ +`ifndef DSP48_NREG_REG +`define DSP48_NREG_REG + +module REG (D, Q, CLK, CE, RESET); + input wire D; + input wire CLK; + input wire CE; + input wire RESET; + output reg Q; + + always @(posedge CLK) begin + if (~RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end + +endmodule // REG + +`endif // `ifndef DSP48_NREG_REG diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg_mux/dreg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg_mux/dreg_mux.pb_type.xml new file mode 100644 index 0000000000..3ce4028cb5 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dreg_mux/dreg_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +DREG_MUX.BYPASS = DREG_MUX.BYPASS +DREG_MUX.REG = DREG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dual_ad_preadder.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dual_ad_preadder.pb_type.xml new file mode 100644 index 0000000000..670b129254 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_ad_preadder/dual_ad_preadder.pb_type.xml @@ -0,0 +1,38 @@ + + .subckt DUAL_AD_PREADDER + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/b1reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/b1reg.pb_type.xml new file mode 100644 index 0000000000..dc0587c95c --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/b1reg.pb_type.xml @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/reg.pb_type.xml new file mode 100644 index 0000000000..8118dafdfd --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg/reg.pb_type.xml @@ -0,0 +1,9 @@ + + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg_mux/b1reg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg_mux/b1reg_mux.pb_type.xml new file mode 100644 index 0000000000..4595cef1ea --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg_mux/b1reg_mux.pb_type.xml @@ -0,0 +1,22 @@ + + + bel + routing + + + + + + + + + bel + routing + +B1REG_MUX.BYPASS = B1REG_MUX.BYPASS +B1REG_MUX.REG = B1REG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/b1reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/b1reg.pb_type.xml new file mode 100644 index 0000000000..dc0587c95c --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/b1reg.pb_type.xml @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/reg.pb_type.xml new file mode 100644 index 0000000000..8118dafdfd --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg/reg.pb_type.xml @@ -0,0 +1,9 @@ + + + .subckt REG + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg_mux/b2reg_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg_mux/b2reg_mux.pb_type.xml new file mode 100644 index 0000000000..9901582df4 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg_mux/b2reg_mux.pb_type.xml @@ -0,0 +1,22 @@ + + + bel + routing + + + + + + + + + bel + routing + +B2REG_MUX.BYPASS = B2REG_MUX.BYPASS +B2REG_MUX.REG = B2REG_MUX.REG + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/bin_mux/bin_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/bin_mux/bin_mux.pb_type.xml new file mode 100644 index 0000000000..f22668a832 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/bin_mux/bin_mux.pb_type.xml @@ -0,0 +1,22 @@ + + + bel + routing + + + + + + + + + bel + routing + +BIN_MUX.B = BIN_MUX.B +BIN_MUX.BCIN = BIN_MUX.BCIN + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/bmult_mux/bmult_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/bmult_mux/bmult_mux.pb_type.xml new file mode 100644 index 0000000000..86fb324004 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/bmult_mux/bmult_mux.pb_type.xml @@ -0,0 +1,19 @@ + + + bel + mux + + .subckt BMULT_MUX + + + + + + + + bel + logic + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/bc_mux/CMakeLists.txt b/xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/CMakeLists.txt similarity index 100% rename from xilinx/common/primitives/dsp48e1/dual_b_reg/bc_mux/CMakeLists.txt rename to xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/CMakeLists.txt diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/bout_mux.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/bout_mux.pb_type.xml new file mode 100644 index 0000000000..ddf966ab2f --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/bout_mux/bout_mux.pb_type.xml @@ -0,0 +1,18 @@ + + + + + + + + + bel + routing + +BOUT_MUX.B1REG = BOUT_MUX.B1REG +BOUT_MUX.B2 = BOUT_MUX.B2 + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dual_b_reg/dual_b_reg.pb_type.xml b/xilinx/common/primitives/dsp48e1/dual_b_reg/dual_b_reg.pb_type.xml new file mode 100644 index 0000000000..1263ca21f4 --- /dev/null +++ b/xilinx/common/primitives/dsp48e1/dual_b_reg/dual_b_reg.pb_type.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/xilinx/common/utils/prjxray_arch_import.py b/xilinx/common/utils/prjxray_arch_import.py index c3a301c47c..ef461b89c0 100644 --- a/xilinx/common/utils/prjxray_arch_import.py +++ b/xilinx/common/utils/prjxray_arch_import.py @@ -521,7 +521,7 @@ def is_in_roi(conn, roi, tile_pkey): "IBUFDS_GTE2": ("Y", 2), "IPAD": (None, None), "OPAD": (None, None), - "DSP48E1": ("X", 2), + "DSP48E1": (None, 2), "TIEOFF": (None, None) } diff --git a/xilinx/common/utils/prjxray_routing_import.py b/xilinx/common/utils/prjxray_routing_import.py index 69f43584d3..4e9560d3f8 100755 --- a/xilinx/common/utils/prjxray_routing_import.py +++ b/xilinx/common/utils/prjxray_routing_import.py @@ -684,7 +684,7 @@ def import_tracks(conn, alive_tracks, node_mapping, graph, default_segment_id): cur2 = conn.cursor() for (graph_node_pkey, track_pkey, graph_node_type, x_low, x_high, y_low, y_high, ptc, capacitance, - resistance) in cur.execute(""" + resistance) in progressbar_utils.progressbar(cur.execute(""" SELECT pkey, track_pkey, @@ -697,7 +697,7 @@ def import_tracks(conn, alive_tracks, node_mapping, graph, default_segment_id): capacitance, resistance FROM - graph_node WHERE track_pkey IS NOT NULL;"""): + graph_node WHERE track_pkey IS NOT NULL;""")): if track_pkey not in alive_tracks: continue @@ -997,7 +997,8 @@ def import_graph_edges(conn, graph, extra_features, node_mapping): nodes_set = set() print('{} Importing edges from database.'.format(now())) - for idx, (src_graph_node, dest_graph_node, switch_pkey, phy_tile_pkey, + with progressbar_utils.ProgressBar(max_value=num_edges) as bar: + for idx, (src_graph_node, dest_graph_node, switch_pkey, phy_tile_pkey, pip_pkey, backward) in enumerate(cur.execute(""" SELECT src_graph_node_pkey, @@ -1095,7 +1096,8 @@ def create_channels(conn): def yield_nodes(nodes): - for idx, node in enumerate(nodes): + with progressbar_utils.ProgressBar(max_value=len(nodes)) as bar: + for idx, node in enumerate(nodes): yield node if idx % 1024 == 0: @@ -1316,8 +1318,8 @@ def main(): args.vpr_capnp_schema_dir, 'rr_graph_uxsdcxx.capnp' ), input_file_name=args.read_rr_graph, - - output_file_name=args.write_rr_graph + progressbar=progressbar_utils.progressbar, + output_file_name=args.write_rr_graph, ) graph = capnp_graph.graph diff --git a/xilinx/xc7/techmap/cells_map.v b/xilinx/xc7/techmap/cells_map.v index f1d74c9f67..68df460cf2 100644 --- a/xilinx/xc7/techmap/cells_map.v +++ b/xilinx/xc7/techmap/cells_map.v @@ -10880,7 +10880,7 @@ module DSP48E1 ( DSP48E1_VPR #( .AREG_0(AREG==0), - .BREG(BREG==0), + .BREG_0(BREG==0), .MASK(MASK), .ADREG(ADREG[0]), .ALUMODEREG(ALUMODEREG[0]), @@ -10910,12 +10910,12 @@ module DSP48E1 ( .PCOUT(PCOUT), .UNDERFLOW(UNDERFLOW), .A(A), - .ACIN(ACIN), + /*.ACIN(ACIN),*/ .ALUMODE(ALUMODE), .B(B), - .BCIN(BCIN), + /*.BCIN(BCIN),*/ .C(C), - .CARRYCASIN(CARRYCASCIN), + /*.CARRYCASCIN(CARRYCASCIN),*/ .CARRYIN(CARRYIN), .CARRYINSEL(CARRYINSEL), .CEA1(CEA1), @@ -10934,9 +10934,9 @@ module DSP48E1 ( .CLK(CLK), .D(D), .INMODE(INMODE), - .MULTSIGNIN(MULTSIGNIN), + /*.MULTSIGNIN(MULTSIGNIN),*/ .OPMODE(OPMODE), - .PCIN(PCIN), + /*.PCIN(PCIN),*/ .RSTA(RSTA), .RSTALLCARRYIN(RSTALLCARRYIN), .RSTALUMODE(RSTALUMODE), diff --git a/xilinx/xc7/techmap/cells_sim.v b/xilinx/xc7/techmap/cells_sim.v index 60ca8d71da..647146c394 100644 --- a/xilinx/xc7/techmap/cells_sim.v +++ b/xilinx/xc7/techmap/cells_sim.v @@ -3610,11 +3610,11 @@ module DSP48E1_VPR ( input RSTALUMODE, input RSTINMODE, input CLK, - input [29:0] ACIN, + /* input [29:0] ACIN, input [17:0] BCIN, input [47:0] PCIN, input CARRYCASCIN, - input MULTSIGNIN, + input MULTSIGNIN,*/ output [29:0] ACOUT, output [17:0] BCOUT, output [47:0] PCOUT, From 83036216cbc121730cbeeaf9259279821970226d Mon Sep 17 00:00:00 2001 From: Abhishek Anand Date: Mon, 3 Jul 2023 12:12:48 +0530 Subject: [PATCH 4/8] Updated dsp48e1 arch def with timing values Signed-off-by: Abhishek Anand --- utils/update_arch_timings.py | 6 +- .../primitives/dsp48e1/dsp48e1.model.xml | 91 +++-- .../primitives/dsp48e1/dsp48e1.pb_type.xml | 370 +++++++++++++++++- xilinx/common/utils/prjxray_arch_import.py | 6 +- xilinx/xc7/bels.json | 48 +++ xilinx/xc7/techmap/cells_map.v | 32 +- xilinx/xc7/techmap/cells_sim.v | 22 +- xilinx/xc7/tests/dsp/top _run1.v | 79 ++++ xilinx/xc7/tests/dsp/top.v | 50 ++- 9 files changed, 616 insertions(+), 88 deletions(-) create mode 100644 xilinx/xc7/tests/dsp/top _run1.v diff --git a/utils/update_arch_timings.py b/utils/update_arch_timings.py index 7aec657e48..a1daa0f218 100755 --- a/utils/update_arch_timings.py +++ b/utils/update_arch_timings.py @@ -114,7 +114,7 @@ def find_timings(timings, bel, location, site, bels, corner, speed_type): def get_timing(cell, delay, corner, speed_type): """ - Gets timing for a particular cornet case. If not fount then chooses + Gets timing for a particular corner case. If not found then chooses the next best one. """ entries = cell[delay]['delay_paths'][corner.lower()] @@ -189,7 +189,9 @@ def get_bel_timings(element, timings, bels, corner, speed_type): bel = pb_chain[-1] location = pb_chain[-2] site = remove_site_number(pb_chain[1]) - + + + result = find_timings( timings, bel, location, site, bels, corner, speed_type ) diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml index 4df1a895c2..26e207c951 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml @@ -1,52 +1,57 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml index 9333cdf932..ac44392df8 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml @@ -1,4 +1,4 @@ - + @@ -32,6 +32,11 @@ + + + + + @@ -45,8 +50,293 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AREG_0=AREG_0 +AREG_2=AREG_2 +A_INPUT[0]=A_INPUT BREG_0=BREG_0 +BREG_2=BREG_2 +B_INPUT[0]=B_INPUT MASK[47:0]=MASK ZADREG[0]=ADREG ZALUMODEREG[0]=ALUMODEREG @@ -81,18 +375,74 @@ ZINMODEREG[0]=INMODEREG ZMREG[0]=MREG ZOPMODEREG[0]=OPMODEREG ZPREG[0]=PREG +ZCREG[0]=CREG ZIS_ALUMODE_INVERTED[3:0]=IS_ALUMODE_INVERTED ZIS_INMODE_INVERTED[4:0]=IS_INMODE_INVERTED -ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED +ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED +ZIS_CLK_INVERTED=IS_CLK_INVERTED +ZIS_CARRYIN_INVERTED=IS_CARRYIN_INVERTED +USE_SIMD_FOUR12_TWO24=USE_SIMD_FOUR12_TWO24 +USE_SIMD_FOUR12=USE_SIMD_FOUR12 +USE_DPORT[0]=USE_DPORT +SEL_MASK_ROUNDING_MODE1=SEL_MASK_ROUNDING_MODE1 +SEL_MASK_ROUNDING_MODE2=SEL_MASK_ROUNDING_MODE2 +SEL_MASK_C=SEL_MASK_C +PATTERN[47:0]=PATTERN +AUTORESET_PATDET_RESET=AUTORESET_PATDET_RESET +AUTORESET_PATDET_RESET_NOT_MATCH=AUTORESET_PATDET_RESET_NOT_MATCH - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - -block -ignore - diff --git a/xilinx/common/utils/prjxray_arch_import.py b/xilinx/common/utils/prjxray_arch_import.py index ef461b89c0..b5ba8cc164 100644 --- a/xilinx/common/utils/prjxray_arch_import.py +++ b/xilinx/common/utils/prjxray_arch_import.py @@ -521,7 +521,7 @@ def is_in_roi(conn, roi, tile_pkey): "IBUFDS_GTE2": ("Y", 2), "IPAD": (None, None), "OPAD": (None, None), - "DSP48E1": (None, 2), + "DSP48E1": (None, None), "TIEOFF": (None, None) } @@ -543,6 +543,8 @@ def make_prefix(site, x, y, from_site_name=False): elif prefix_required[0] == 'XY': mod_x, mod_y = prefix_required[1] return site_type, '{}_X{}Y{}'.format(site_type, x % mod_x, y % mod_y) + elif site_type == 'DSP48E1': + return site_type, '{}.{}_{}'.format("DSP48", "DSP", y % 2) elif prefix_required[0] is None: return site_type, None else: @@ -610,7 +612,7 @@ def create_capacity_prefix(c, tile_prefix, tile_pkey, tile_capacity): (tile_pkey, ) ) - NO_SITE_TYPE_PREFIX = ["SLICEL", "SLICEM", "IBUFDS_GTE2"] + NO_SITE_TYPE_PREFIX = ["SLICEL", "SLICEM", "IBUFDS_GTE2", "DSP48E1"] prefixes = [] diff --git a/xilinx/xc7/bels.json b/xilinx/xc7/bels.json index 91b85ca607..6b38c0469b 100644 --- a/xilinx/xc7/bels.json +++ b/xilinx/xc7/bels.json @@ -297,5 +297,53 @@ "OLOGICE3_TFF_SAMEEDGE.OLOGICE3" ] } + }, + "DSP": { + "DSP": { + "DSP48": [ + "DSP48E1_ADREG_0_AREG_0_A_INPUT_DIRECT_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_BREG_0_B_INPUT_DIRECT_MREG_0_PREG_1_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_CREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_OPMODEREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_ALUMODEREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_CARRYINREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_CARRYINSELREG_0_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_INMODEREG_0_MREG_0_PREG_1_USE_DPORT_FALSE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_AREG_2.DSP48E1", + "DSP48E1_BREG_2.DSP48E1", + "DSP48E1_CREG_1.DSP48E1", + "DSP48E1_DREG_1.DSP48E1", + "DSP48E1_MREG_1.DSP48E1", + "DSP48E1_PREG_1.DSP48E1", + "DSP48E1_ADREG_1.DSP48E1", + "DSP48E1_ALUMODEREG_1.DSP48E1", + "DSP48E1_CARRYINSELREG_1.DSP48E1", + "DSP48E1_CARRYINREG_1.DSP48E1", + "DSP48E1_INMODEREG_1.DSP48E1", + "DSP48E1_ADREG_0_AREG_0_A_INPUT_CASCADE_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_BREG_0_B_INPUT_CASCADE_MREG_0_PREG_1_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_PREG_1_USE_PATTERN_DETECT_NO_PATDET.DSP48E1", + "DSP48E1_ACASCREG_2_AREG_2.DSP48E1", + "DSP48E1_BCASCREG_2_BREG_2.DSP48E1", + "DSP48E1_BREG_1_MREG_0_PREG_0_USE_MULT_MULTIPLY.DSP48E1", + "DSP48E1_ACASCREG_0_A_INPUT_CASCADE.DSP48E1", + "DSP48E1_ACASCREG_0_A_INPUT_DIRECT.DSP48E1", + "DSP48E1_ADREG_0_AREG_0_A_INPUT_CASCADE_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1", + "DSP48E1_ADREG_0_AREG_0_A_INPUT_DIRECT_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1", + "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1", + "DSP48E1_ADREG_0_INMODEREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY.DSP48E1", + "DSP48E1_ALUMODEREG_0_PREG_0.DSP48E1", + "DSP48E1_BCASCREG_0_B_INPUT_CASCADE.DSP48E1", + "DSP48E1_BCASCREG_0_B_INPUT_DIRECT.DSP48E1", + "DSP48E1_BREG_0_B_INPUT_CASCADE_MREG_0_PREG_0_USE_MULT_DYNAMIC.DSP48E1", + "DSP48E1_BREG_0_B_INPUT_DIRECT_MREG_0_PREG_0_USE_MULT_DYNAMIC.DSP48E1", + "DSP48E1_CARRYINREG_0_PREG_0.DSP48E1", + "DSP48E1_CARRYINSELREG_0_PREG_0.DSP48E1", + "DSP48E1_CREG_0_PREG_0.DSP48E1", + "DSP48E1_OPMODEREG_0_PREG_0.DSP48E1", + "DSP48E1_PREG_0.DSP48E1" + ] + } } } diff --git a/xilinx/xc7/techmap/cells_map.v b/xilinx/xc7/techmap/cells_map.v index 68df460cf2..fd9973a38c 100644 --- a/xilinx/xc7/techmap/cells_map.v +++ b/xilinx/xc7/techmap/cells_map.v @@ -10881,11 +10881,13 @@ module DSP48E1 ( .AREG_0(AREG==0), .BREG_0(BREG==0), + .AREG_2(AREG==2), + .BREG_2(BREG==2), .MASK(MASK), .ADREG(ADREG[0]), .ALUMODEREG(ALUMODEREG[0]), - .ACASCREG(ACASCREG[0]), - .BCASCREG(BCASCREG[0]), + .ACASCREG(AREG==2 && ACASCREG==1), + .BCASCREG(BREG==2 && BCASCREG==1), .CARRYINREG(CARRYINREG[0]), .CARRYINSELREG(CARRYINSELREG[0]), .DREG(DREG[0]), @@ -10895,7 +10897,21 @@ module DSP48E1 ( .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED), .MREG(MREG[0]), .OPMODEREG(OPMODEREG[0]), - .PREG(PREG[0]) + .PREG(PREG[0]), + .CREG(CREG[0]), + .A_INPUT(A_INPUT == "CASCADE"), + .B_INPUT(B_INPUT == "CASCADE"), + .USE_DPORT(USE_DPORT == "TRUE"), + .USE_SIMD_FOUR12(USE_SIMD == "FOUR12"), + .USE_SIMD_FOUR12_TWO24(USE_SIMD == "TWO24"), + .AUTORESET_PATDET_RESET(AUTORESET_PATDET == "RESET_MATCH"), + .AUTORESET_PATDET_RESET_NOT_MATCH(AUTORESET_PATDET == "RESET_NOT_MATCH"), + .PATTERN(PATTERN), + .SEL_MASK_ROUNDING_MODE1(SEL_MASK == "ROUNDING_MODE1"), + .SEL_MASK_ROUNDING_MODE2(SEL_MASK == "ROUNDING_MODE2"), + .SEL_MASK_C(SEL_MASK == "C"), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED) ) _TECHMAP_REPLACE_ ( .ACOUT(ACOUT), @@ -10910,12 +10926,12 @@ module DSP48E1 ( .PCOUT(PCOUT), .UNDERFLOW(UNDERFLOW), .A(A), - /*.ACIN(ACIN),*/ + .ACIN(ACIN), .ALUMODE(ALUMODE), .B(B), - /*.BCIN(BCIN),*/ + .BCIN(BCIN), .C(C), - /*.CARRYCASCIN(CARRYCASCIN),*/ + .CARRYCASCIN(CARRYCASCIN), .CARRYIN(CARRYIN), .CARRYINSEL(CARRYINSEL), .CEA1(CEA1), @@ -10934,9 +10950,9 @@ module DSP48E1 ( .CLK(CLK), .D(D), .INMODE(INMODE), - /*.MULTSIGNIN(MULTSIGNIN),*/ + .MULTSIGNIN(MULTSIGNIN), .OPMODE(OPMODE), - /*.PCIN(PCIN),*/ + .PCIN(PCIN), .RSTA(RSTA), .RSTALLCARRYIN(RSTALLCARRYIN), .RSTALUMODE(RSTALUMODE), diff --git a/xilinx/xc7/techmap/cells_sim.v b/xilinx/xc7/techmap/cells_sim.v index 647146c394..e25ca25026 100644 --- a/xilinx/xc7/techmap/cells_sim.v +++ b/xilinx/xc7/techmap/cells_sim.v @@ -3610,11 +3610,11 @@ module DSP48E1_VPR ( input RSTALUMODE, input RSTINMODE, input CLK, - /* input [29:0] ACIN, + input [29:0] ACIN, input [17:0] BCIN, input [47:0] PCIN, input CARRYCASCIN, - input MULTSIGNIN,*/ + input MULTSIGNIN, output [29:0] ACOUT, output [17:0] BCOUT, output [47:0] PCOUT, @@ -3629,7 +3629,10 @@ module DSP48E1_VPR ( ); parameter AREG_0 = 1'b0; parameter BREG_0 = 1'b0; - parameter MASK = 46'b0000000000000000000000000000000000000000000000; + parameter AREG_2 = 1'b0; + parameter BREG_2 = 1'b0; + parameter MASK = 48'b000000000000000000000000000000000000000000000000; + parameter PATTERN = 48'b000000000000000000000000000000000000000000000000; parameter ADREG = 1'b0; parameter ALUMODEREG = 1'b0; parameter ACASCREG = 1'b0; @@ -3641,7 +3644,20 @@ module DSP48E1_VPR ( parameter MREG = 1'b0; parameter OPMODEREG = 1'b0; parameter PREG = 1'b0; + parameter CREG = 1'b0; + parameter A_INPUT = 1'b0; + parameter B_INPUT = 1'b0; + parameter USE_DPORT = 1'b0; + parameter USE_SIMD_FOUR12 = 1'b0; + parameter USE_SIMD_FOUR12_TWO24 = 1'b0; + parameter AUTORESET_PATDET_RESET = 1'b0; + parameter AUTORESET_PATDET_RESET_NOT_MATCH = 1'b0; + parameter SEL_MASK_ROUNDING_MODE1 = 1'b0; + parameter SEL_MASK_ROUNDING_MODE2 = 1'b0; + parameter SEL_MASK_C = 1'b0; parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + parameter IS_CARRYIN_INVERTED = 1'b0; + parameter IS_CLK_INVERTED = 1'b0; endmodule diff --git a/xilinx/xc7/tests/dsp/top _run1.v b/xilinx/xc7/tests/dsp/top _run1.v new file mode 100644 index 0000000000..7ad8dc78e8 --- /dev/null +++ b/xilinx/xc7/tests/dsp/top _run1.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps + +module top + ( + A, + B, + OUT + ); + + + (* IOSTANDARD = "LVCMOS33" *) input wire [24:0] A; + (* IOSTANDARD = "LVCMOS33" *) input wire [17:0] B; + (* IOSTANDARD = "LVCMOS33" *) output wire [16:0] OUT; + + + DSP48E1 #( + .AREG(1'b0), + .BREG(1'b0), + .MASK(48'b111111111111111111111111111111111111111111111111), + /* .ADREG(), + .ALUMODEREG(), + .ACASCREG(), + .BCASCREG(), + .CARRYINREG(), + .CARRYINSELREG(), + .DREG(), + .INMODEREG(), */ + .IS_ALUMODE_INVERTED(4'b1100), + .IS_INMODE_INVERTED(5'b11111), + .IS_OPMODE_INVERTED(7'b1000101), + /* .MREG(), + .OPMODEREG(), + .PREG() */ + ) + dsp25x18( + .A(A), + .ACIN(30'b000000000000000000000000000000), + .ALUMODE(4'b0011), + .B(B), + .BCIN(18'b000000000000000000), + .C(48'b111111111111111111111111111111111111111111111111), + .CARRYCASCIN(1'b0), + .CARRYIN(1'b0), + .CARRYINSEL(3'b000), + .CEA1(1'b0), + .CEA2(1'b0), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(1'b0), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(1'b0), + .CEP(1'b0), + .CLK(1'b0), + .D(25'b0000000000000000000000000), + .INMODE(5'b00000), + .MULTSIGNIN(1'b0), + .OPMODE(7'b0111111), + .PCIN(48'b000000000000000000000000000000000000000000000000), + .RSTA(1'b0), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(1'b0), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(1'b0), + .RSTP(1'b0), + .P(OUT) + ); + + + +endmodule // MULT25X18 diff --git a/xilinx/xc7/tests/dsp/top.v b/xilinx/xc7/tests/dsp/top.v index 7ad8dc78e8..6832cf3c95 100644 --- a/xilinx/xc7/tests/dsp/top.v +++ b/xilinx/xc7/tests/dsp/top.v @@ -14,32 +14,42 @@ module top DSP48E1 #( - .AREG(1'b0), - .BREG(1'b0), - .MASK(48'b111111111111111111111111111111111111111111111111), - /* .ADREG(), - .ALUMODEREG(), - .ACASCREG(), - .BCASCREG(), - .CARRYINREG(), - .CARRYINSELREG(), - .DREG(), - .INMODEREG(), */ - .IS_ALUMODE_INVERTED(4'b1100), + .AREG(2'b10), + .BREG(2'b10), + .MASK(48'b111110111111101111111111100001111011110111111101), + .ADREG(1'b0), + .ALUMODEREG(1'b0), + .ACASCREG(1'b1), + .BCASCREG(1'b1), + .CARRYINREG(1'b0), + .CARRYINSELREG(1'b0), + .DREG(1'b0), + .INMODEREG(1'b0), + .IS_ALUMODE_INVERTED(4'b1101), .IS_INMODE_INVERTED(5'b11111), .IS_OPMODE_INVERTED(7'b1000101), - /* .MREG(), - .OPMODEREG(), - .PREG() */ + .MREG(1'b0), + .OPMODEREG(1'b0), + .PREG(1'b0), + .CREG(1'b0), + .A_INPUT("CASCADE"), + .B_INPUT("CASCADE"), + .USE_DPORT("TRUE"), + .USE_SIMD("FOUR12"), + .AUTORESET_PATDET("RESET_MATCH"), + .PATTERN(48'b111110111111101111111111100001111011110111111101), + .SEL_MASK("ROUNDING_MODE1"), + .IS_CARRYIN_INVERTED(1'b1), + .IS_CLK_INVERTED(1'b1) ) dsp25x18( .A(A), - .ACIN(30'b000000000000000000000000000000), + .ALUMODE(4'b0011), .B(B), - .BCIN(18'b000000000000000000), + .C(48'b111111111111111111111111111111111111111111111111), - .CARRYCASCIN(1'b0), + .CARRYIN(1'b0), .CARRYINSEL(3'b000), .CEA1(1'b0), @@ -58,9 +68,9 @@ module top .CLK(1'b0), .D(25'b0000000000000000000000000), .INMODE(5'b00000), - .MULTSIGNIN(1'b0), + .OPMODE(7'b0111111), - .PCIN(48'b000000000000000000000000000000000000000000000000), + .RSTA(1'b0), .RSTALLCARRYIN(1'b0), .RSTALUMODE(1'b0), From de5533190b9d9e18ff455e5b3d9de716cc1282f3 Mon Sep 17 00:00:00 2001 From: Abhishek Anand Date: Wed, 5 Jul 2023 21:38:33 +0530 Subject: [PATCH 5/8] Included internal combinational delays in dsp48e1 primitive Signed-off-by: Abhishek Anand --- .../primitives/dsp48e1/dsp48e1.model.xml | 28 +++---- .../primitives/dsp48e1/dsp48e1.pb_type.xml | 35 +++++++- xilinx/xc7/techmap/cells_map.v | 10 +-- xilinx/xc7/tests/dsp/top _run1.v | 79 ------------------- xilinx/xc7/tests/dsp/top.v | 22 ++---- 5 files changed, 60 insertions(+), 114 deletions(-) delete mode 100644 xilinx/xc7/tests/dsp/top _run1.v diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml index 26e207c951..8148752720 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.model.xml @@ -1,15 +1,15 @@ - - - - - - - - - + + + + + + + + + @@ -34,11 +34,11 @@ - - - - - + + + + + diff --git a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml index ac44392df8..889baa4cb8 100644 --- a/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml +++ b/xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml @@ -235,7 +235,7 @@ - + @@ -336,6 +336,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +