From 6ad7ab91e16ace40c1db423c50b97b1f19c97d15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Denkinger?= Date: Tue, 28 Nov 2023 11:57:41 +0100 Subject: [PATCH] Renaming all cgra_x_heep reference to heepsilon. --- Makefile | 2 +- cgra_x_heep.core => heepsilon.core | 10 +- heepsilon_cfg.hjson | 4 +- ...wrapper.sv => xilinx_heepsilon_wrapper.sv} | 6 +- hw/rtl/cgra_top.vlt | 2 +- ...x_heep_pkg.sv.tpl => heepsilon_pkg.sv.tpl} | 4 +- .../{cgra_x_heep_top.sv => heepsilon_top.sv} | 14 +- hw/vendor/esl_epfl_cgra/lint/cgra.vlt | 16 +- .../docs/source/How_to/eXtendingHEEP.md | 2 +- scripts/sim/modelsim/log_cgra_waves.do | 174 +++++++++--------- .../sim/modelsim/patch_modelsim_Makefile.py | 2 +- sw/applications/cgra_check_conf/main.c | 2 +- sw/applications/cgra_dbl_search/main.c | 2 +- sw/applications/cgra_fft/main.c | 2 +- sw/applications/cgra_func_test/main.c | 2 +- .../kernels_common/kernels_common.h | 2 +- sw/external/drivers/cgra/cgra.c | 2 +- .../extensions/{cgra_x_heep.h => heepsilon.h} | 0 tb/tb_util.svh.tpl | 42 ++--- tb/testharness.sv | 29 +-- 20 files changed, 160 insertions(+), 159 deletions(-) rename cgra_x_heep.core => heepsilon.core (97%) rename hw/fpga_cgra/{xilinx_cgra_x_heep_wrapper.sv => xilinx_heepsilon_wrapper.sv} (97%) rename hw/rtl/{cgra_x_heep_pkg.sv.tpl => heepsilon_pkg.sv.tpl} (97%) rename hw/rtl/{cgra_x_heep_top.sv => heepsilon_top.sv} (95%) rename sw/external/extensions/{cgra_x_heep.h => heepsilon.h} (100%) diff --git a/Makefile b/Makefile index f9a7fa6e..9c6f70c5 100644 --- a/Makefile +++ b/Makefile @@ -28,7 +28,7 @@ heepsilon-gen: $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --pkg-sv hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --tpl-sv hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/util --tpl-sv hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl - $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/rtl --pkg-sv hw/rtl/cgra_x_heep_pkg.sv.tpl + $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/rtl --pkg-sv hw/rtl/heepsilon_pkg.sv.tpl $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir sw/external/drivers/cgra --header-c sw/external/drivers/cgra/cgra.h.tpl $(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/data --pkg-sv hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl bash -c "cd hw/vendor/esl_epfl_cgra/data; source cgra_reg_gen.sh; cd ../../../.." diff --git a/cgra_x_heep.core b/heepsilon.core similarity index 97% rename from cgra_x_heep.core rename to heepsilon.core index d828a37c..456d4b16 100644 --- a/cgra_x_heep.core +++ b/heepsilon.core @@ -14,8 +14,8 @@ filesets: - openhwgroup.org:systems:core-v-mini-mcu - eslepfl::cgra files: - - hw/rtl/cgra_x_heep_pkg.sv - - hw/rtl/cgra_x_heep_top.sv + - hw/rtl/heepsilon_pkg.sv + - hw/rtl/heepsilon_top.sv file_type: systemVerilogSource x_heep_system: @@ -102,7 +102,7 @@ filesets: - hw/fpga/sram_wrapper.sv - hw/fpga_cgra/cgra_sram_wrapper.sv - hw/fpga_cgra/cgra_clock_gate.sv - - hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv + - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv file_type: systemVerilogSource ip-fpga: @@ -179,7 +179,7 @@ targets: default: &default_target filesets: - files_rtl_generic - toplevel: [cgra_x_heep_top] + toplevel: [heepsilon_top] sim: <<: *default_target @@ -277,4 +277,4 @@ targets: tools: vivado: part: xc7z020clg400-1 - toplevel: [xilinx_cgra_x_heep_wrapper] \ No newline at end of file + toplevel: [xilinx_heepsilon_wrapper] \ No newline at end of file diff --git a/heepsilon_cfg.hjson b/heepsilon_cfg.hjson index e09aa144..53a96542 100644 --- a/heepsilon_cfg.hjson +++ b/heepsilon_cfg.hjson @@ -10,10 +10,10 @@ // This limit can be increased but manual changes are required // Maximum number of columns: 32-log2(rcs_num_instr)-log2(max_columns*rcs_num_instr) // Default settings enable: 32-log2(32)-log2(4*32) = 20 columns - num_columns: 4 + num_columns: 11 // Main impact: more rows equals to more context memory banks (i.e., one per row) // There should be no limitation compared to the number of rows compared to columns - num_rows: 4 + num_rows: 5 // It is possible to limit the maximum number of columns a kernel can use (this saves a bit of ressources) // The default value should be the same than num_columns, put an number to change it max_columns: default diff --git a/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv b/hw/fpga_cgra/xilinx_heepsilon_wrapper.sv similarity index 97% rename from hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv rename to hw/fpga_cgra/xilinx_heepsilon_wrapper.sv index ca4f6ab4..18002a2c 100644 --- a/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv +++ b/hw/fpga_cgra/xilinx_heepsilon_wrapper.sv @@ -2,7 +2,7 @@ // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -module xilinx_cgra_x_heep_wrapper +module xilinx_heepsilon_wrapper import obi_pkg::*; import reg_pkg::*; #( @@ -89,11 +89,11 @@ module xilinx_cgra_x_heep_wrapper .clk_out1_0(clk_gen) ); - cgra_x_heep_top #( + heepsilon_top #( .COREV_PULP (0), .FPU (0), .ZFINX (0) - ) cgra_x_heep_top_i ( + ) heepsilon_top_i ( .clk_i(clk_gen), .rst_ni(rst_n), .boot_select_i, diff --git a/hw/rtl/cgra_top.vlt b/hw/rtl/cgra_top.vlt index 63a62561..1ee224fd 100644 --- a/hw/rtl/cgra_top.vlt +++ b/hw/rtl/cgra_top.vlt @@ -4,4 +4,4 @@ `verilator_config -lint_off -rule UNUSED -file "*hw/rtl/cgra_x_heep_top.sv" -match "Signal is not used: 'external_subsystem_powergate_iso'*" +lint_off -rule UNUSED -file "*hw/rtl/heepsilon_top.sv" -match "Signal is not used: 'external_subsystem_powergate_iso'*" diff --git a/hw/rtl/cgra_x_heep_pkg.sv.tpl b/hw/rtl/heepsilon_pkg.sv.tpl similarity index 97% rename from hw/rtl/cgra_x_heep_pkg.sv.tpl rename to hw/rtl/heepsilon_pkg.sv.tpl index 5889a580..4de3b2b8 100644 --- a/hw/rtl/cgra_x_heep_pkg.sv.tpl +++ b/hw/rtl/heepsilon_pkg.sv.tpl @@ -2,7 +2,7 @@ // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -package cgra_x_heep_pkg; +package heepsilon_pkg; import addr_map_rule_pkg::*; import core_v_mini_mcu_pkg::*; @@ -49,4 +49,4 @@ package cgra_x_heep_pkg; EXT_SYSTEM_NPERIPHERALS ) : 32'd1; -endpackage // cgra_x_heep_pkg +endpackage // heepsilon_pkg diff --git a/hw/rtl/cgra_x_heep_top.sv b/hw/rtl/heepsilon_top.sv similarity index 95% rename from hw/rtl/cgra_x_heep_top.sv rename to hw/rtl/heepsilon_top.sv index beb90900..c8497c26 100644 --- a/hw/rtl/cgra_x_heep_top.sv +++ b/hw/rtl/heepsilon_top.sv @@ -2,7 +2,7 @@ // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -module cgra_x_heep_top #( +module heepsilon_top #( parameter COREV_PULP = 0, parameter FPU = 0, parameter ZFINX = 0, @@ -49,17 +49,17 @@ module cgra_x_heep_top #( import obi_pkg::*; import reg_pkg::*; - import cgra_x_heep_pkg::*; + import heepsilon_pkg::*; // External xbar master/slave and peripheral ports obi_req_t ext_xbar_slave_req; obi_resp_t ext_xbar_slave_resp; reg_req_t ext_periph_slave_req; reg_rsp_t ext_periph_slave_resp; - obi_req_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_req; - obi_req_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_req; - obi_resp_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_resp; - obi_resp_t [cgra_x_heep_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_resp; + obi_req_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_req; + obi_req_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_req; + obi_resp_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] ext_master_resp; + obi_resp_t [heepsilon_pkg::CGRA_XBAR_NMASTER-1:0] heep_slave_resp; obi_req_t heep_core_instr_req; obi_resp_t heep_core_instr_resp; obi_req_t heep_core_data_req; @@ -262,4 +262,4 @@ module cgra_x_heep_top #( .external_ram_banks_set_retentive_no(external_ram_banks_set_retentive) ); -endmodule // cgra_x_heep_pkg +endmodule // heepsilon_pkg diff --git a/hw/vendor/esl_epfl_cgra/lint/cgra.vlt b/hw/vendor/esl_epfl_cgra/lint/cgra.vlt index c7410e9e..0adeb55c 100644 --- a/hw/vendor/esl_epfl_cgra/lint/cgra.vlt +++ b/hw/vendor/esl_epfl_cgra/lint/cgra.vlt @@ -47,14 +47,14 @@ lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signa lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'shift_right_result_33b'[32]" // The tool detect multiple drivers at the same line of code (the tool does not interpret the for loop correctly?) -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*" -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*" -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*" -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*" -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*" -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*" - -lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*" +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*" + +lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*" // Remove clock gating instance for verilator simulation otherwise sim is failing (verilator v4.2) lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/cgra_top.sv" -match "Signal is not used: 'rcs_col_e_s'" diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md index ad8805b1..cca7492b 100644 --- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md +++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md @@ -8,7 +8,7 @@ For this purpose we support the [CORE-V-XIF](https://docs.openhwgroup.org/projec Here you can find a list of `X-HEEP` based open-source examples. If you want to include your project in this list, please open an issue with a link to your repository. -* [CGRA-X-HEEP](https://github.com/esl-epfl/cgra_x_heep): A CGRA loosely coupled with X-HEEP. +* [CGRA-X-HEEP](https://github.com/esl-epfl/heepsilon): A CGRA loosely coupled with X-HEEP. * [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x. diff --git a/scripts/sim/modelsim/log_cgra_waves.do b/scripts/sim/modelsim/log_cgra_waves.do index 70bfe0de..eda89c94 100644 --- a/scripts/sim/modelsim/log_cgra_waves.do +++ b/scripts/sim/modelsim/log_cgra_waves.do @@ -1,93 +1,93 @@ -log -r tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/* -nofilter Memory +log -r tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/* -nofilter Memory onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/clk_i -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/rst_ni -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_instr_req_o -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_instr_resp_i -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_data_req_o -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_data_resp_i -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_i -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_ack_o -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_id_o -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/debug_req_i -add wave -noupdate -group CPU /tb_top/testharness_i/cgra_x_heep_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_sleep_o -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/clk_i -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/rst_ni -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/rst_logic_ni -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_enable_i -add wave -noupdate -group CGRA_TOP_WRAPPER -subitemconfig {{/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_req_o[1]} -expand {/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_req_o[0]} -expand} /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_req_o -add wave -noupdate -group CGRA_TOP_WRAPPER -subitemconfig {{/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_resp_i[1]} -expand {/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_resp_i[0]} -expand} /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/masters_resp_i -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/reg_req_i -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/reg_rsp_o -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/slave_req_i -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/slave_resp_o -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cmem_set_retentive_i -add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_int_o -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/clk_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/rst_ni -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_cg_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_set_retentive_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_row_req_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_we_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_addr_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_wdata_i -add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_context_memory_i/rcs_cmem_rdata_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/clk_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rst_ni -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_req_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_gnt_ctrl_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_rvalid_ctrl_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/kmem_rdata_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/ker_id_req_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/data_stall_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_br_req_i -add wave -noupdate -group CGRA_CTRL -expand /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_br_add_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_stall_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_exec_end_i -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_we_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_re_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_pc_e_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_pc_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/col_e_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_rst_col_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_ack_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_radd_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_req_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/col_start_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_ack_o -add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_end_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/clk_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rst_col_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_we_i -add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_re_i -add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_col_pc_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_words_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_pc_e_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_rdata_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_gnt_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_rvalid_i -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_wen_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_ind_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_add_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_wdata_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_br_add_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_stall_o -add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/exec_end_o -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_stall_s -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_nop_s -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_stall_col -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_gnt_mask -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_rvalid_mask -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rvalid_demux -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/gnt_mask -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rvalid_mask -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_res -add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_res_reg -add wave -noupdate -group RC_2_1 -expand {/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_row_gen[2]/rc_col_gen[1]/rc_i/rc_datapath/reg_file_i/regs_o} -add wave -noupdate -group RC_3_1 -expand {/tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_row_gen[3]/rc_col_gen[1]/rc_i/rc_datapath/reg_file_i/regs_o} +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/clk_i +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/rst_ni +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_instr_req_o +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_instr_resp_i +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_data_req_o +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_data_resp_i +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_i +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_ack_o +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/irq_id_o +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/debug_req_i +add wave -noupdate -group CPU /tb_top/testharness_i/heepsilon_top_i/x_heep_system_i/core_v_mini_mcu_i/cpu_subsystem_i/core_sleep_o +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/clk_i +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/rst_ni +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/rst_logic_ni +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_enable_i +add wave -noupdate -group CGRA_TOP_WRAPPER -subitemconfig {{/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_req_o[1]} -expand {/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_req_o[0]} -expand} /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_req_o +add wave -noupdate -group CGRA_TOP_WRAPPER -subitemconfig {{/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_resp_i[1]} -expand {/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_resp_i[0]} -expand} /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/masters_resp_i +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/reg_req_i +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/reg_rsp_o +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/slave_req_i +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/slave_resp_o +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cmem_set_retentive_i +add wave -noupdate -group CGRA_TOP_WRAPPER /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_int_o +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/clk_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/rst_ni +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_cg_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_set_retentive_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_row_req_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_we_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_addr_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/cm_wdata_i +add wave -noupdate -group CGRA_CONTEXT_MEM /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_context_memory_i/rcs_cmem_rdata_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/clk_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rst_ni +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_req_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_gnt_ctrl_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_rvalid_ctrl_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/kmem_rdata_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/ker_id_req_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/data_stall_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_br_req_i +add wave -noupdate -group CGRA_CTRL -expand /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_br_add_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_stall_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_exec_end_i +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_we_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_re_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_pc_e_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_pc_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/col_e_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_rst_col_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_ack_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/imem_radd_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/rcs_conf_req_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/col_start_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_ack_o +add wave -noupdate -group CGRA_CTRL /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_ctrl_i/acc_end_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/clk_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rst_col_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_we_i +add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_re_i +add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_col_pc_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_conf_words_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_pc_e_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_rdata_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_gnt_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_rvalid_i +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_wen_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_ind_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_add_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_wdata_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_br_add_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_stall_o +add wave -noupdate -group CGRA_RCS -expand /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/exec_end_o +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_stall_s +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_nop_s +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_stall_col +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_gnt_mask +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/data_req_rvalid_mask +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rvalid_demux +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/gnt_mask +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rvalid_mask +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_res +add wave -noupdate -group CGRA_RCS /tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rcs_res_reg +add wave -noupdate -group RC_2_1 -expand {/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_row_gen[2]/rc_col_gen[1]/rc_i/rc_datapath/reg_file_i/regs_o} +add wave -noupdate -group RC_3_1 -expand {/tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i/cgra_top_i/cgra_rcs_i/rc_row_gen[3]/rc_col_gen[1]/rc_i/rc_datapath/reg_file_i/regs_o} TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {4943608936 ps} 0} quietly wave cursor active 1 diff --git a/scripts/sim/modelsim/patch_modelsim_Makefile.py b/scripts/sim/modelsim/patch_modelsim_Makefile.py index dd7a7ce1..052f9cbc 100644 --- a/scripts/sim/modelsim/patch_modelsim_Makefile.py +++ b/scripts/sim/modelsim/patch_modelsim_Makefile.py @@ -81,7 +81,7 @@ # Fix the ocurrences of hw/hw/ inside the edalize_build_rtl.tcl file data = data.replace("/hw/hw/","/hw/") -instance = "tb_top/testharness_i/cgra_x_heep_top_i/cgra_top_wrapper_i" +instance = "tb_top/testharness_i/heepsilon_top_i/cgra_top_wrapper_i" data = data + "\n\nvsim -vcddump -r tb_top\n" data = data + "vsim -saifdump dump.saif tb_top\n" diff --git a/sw/applications/cgra_check_conf/main.c b/sw/applications/cgra_check_conf/main.c index adc467be..7892fe63 100644 --- a/sw/applications/cgra_check_conf/main.c +++ b/sw/applications/cgra_check_conf/main.c @@ -14,7 +14,7 @@ #include "core_v_mini_mcu.h" #include "rv_plic.h" #include "rv_plic_regs.h" -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "cgra.h" #define DEBUG diff --git a/sw/applications/cgra_dbl_search/main.c b/sw/applications/cgra_dbl_search/main.c index 810d585b..e46890fa 100644 --- a/sw/applications/cgra_dbl_search/main.c +++ b/sw/applications/cgra_dbl_search/main.c @@ -7,7 +7,7 @@ #include "core_v_mini_mcu.h" #include "rv_plic.h" #include "rv_plic_regs.h" -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "cgra.h" #include "cgra_bitstream.h" #include "stimuli.h" diff --git a/sw/applications/cgra_fft/main.c b/sw/applications/cgra_fft/main.c index 2e31236a..4703b49b 100644 --- a/sw/applications/cgra_fft/main.c +++ b/sw/applications/cgra_fft/main.c @@ -7,7 +7,7 @@ #include "core_v_mini_mcu.h" #include "rv_plic.h" #include "rv_plic_regs.h" -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "cgra.h" #include "cgra_bitstream.h" #include "fxp.h" diff --git a/sw/applications/cgra_func_test/main.c b/sw/applications/cgra_func_test/main.c index fb2dbb94..9cd8b063 100644 --- a/sw/applications/cgra_func_test/main.c +++ b/sw/applications/cgra_func_test/main.c @@ -7,7 +7,7 @@ #include "core_v_mini_mcu.h" #include "rv_plic.h" #include "rv_plic_regs.h" -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "cgra.h" #include "cgra_bitstream.h" #include "fxp.h" diff --git a/sw/applications/kernel_test/kernels_common/kernels_common.h b/sw/applications/kernel_test/kernels_common/kernels_common.h index e98261c2..ee5c2894 100644 --- a/sw/applications/kernel_test/kernels_common/kernels_common.h +++ b/sw/applications/kernel_test/kernels_common/kernels_common.h @@ -39,7 +39,7 @@ #include #include "cgra.h" -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "hart.h" #include diff --git a/sw/external/drivers/cgra/cgra.c b/sw/external/drivers/cgra/cgra.c index 4de4c320..40aeb1a2 100644 --- a/sw/external/drivers/cgra/cgra.c +++ b/sw/external/drivers/cgra/cgra.c @@ -5,7 +5,7 @@ #include #include -#include "cgra_x_heep.h" +#include "heepsilon.h" #include "core_v_mini_mcu.h" #include "cgra.h" #include "cgra_regs.h" // generated diff --git a/sw/external/extensions/cgra_x_heep.h b/sw/external/extensions/heepsilon.h similarity index 100% rename from sw/external/extensions/cgra_x_heep.h rename to sw/external/extensions/heepsilon.h diff --git a/tb/tb_util.svh.tpl b/tb/tb_util.svh.tpl index 60fed273..960ca080 100644 --- a/tb/tb_util.svh.tpl +++ b/tb/tb_util.svh.tpl @@ -40,36 +40,36 @@ task tb_loadHEX; `ifndef VERILATOR for (i = 0; i < NumBytes; i = i + 4) begin - @(posedge cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.clk_i); + @(posedge heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.clk_i); addr = i; #1; // write to memory - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o = 1'b1; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_addr_o = addr; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_we_o = 1'b1; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_be_o = 4'b1111; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_wdata_o = { + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o = 1'b1; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_addr_o = addr; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_we_o = 1'b1; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_be_o = 4'b1111; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_wdata_o = { stimuli[i+3], stimuli[i+2], stimuli[i+1], stimuli[i] }; - wait (cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_gnt_i); + wait (heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_gnt_i); - @(posedge cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.clk_i); + @(posedge heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.clk_i); #1; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o = 1'b0; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o = 1'b0; - wait (cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_rvalid_i); + wait (heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_rvalid_i); #1; end - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_addr_o; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_we_o; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_be_o; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_wdata_o; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_req_o; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_addr_o; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_we_o; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_be_o; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_wdata_o; `else @@ -94,12 +94,12 @@ task tb_writetoSram${bank}; input [7:0] val1; input [7:0] val0; `ifdef VCS - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = { + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = { val3, val2, val1, val0 }; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr]; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr]; `else - cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = { + heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = { val3, val2, val1, val0 }; `endif @@ -109,10 +109,10 @@ endtask task tb_set_exit_loop; `ifdef VCS - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0] = 1'b1; - release cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0]; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0] = 1'b1; + release heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0]; `else - cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0] = 1'b1; + heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.ao_peripheral_subsystem_i.soc_ctrl_i.testbench_set_exit_loop[0] = 1'b1; `endif endtask `endif diff --git a/tb/testharness.sv b/tb/testharness.sv index aea1ddc1..f982ffd4 100644 --- a/tb/testharness.sv +++ b/tb/testharness.sv @@ -7,6 +7,7 @@ module testharness #( parameter FPU = 0, parameter ZFINX = 0, parameter X_EXT = 0, + parameter USE_EXTERNAL_DEVICE_EXAMPLE = 0, parameter JTAG_DPI = 0, parameter CLK_FREQUENCY = 'd100_000 //KHz ) ( @@ -55,12 +56,12 @@ module testharness #( logic external_subsystem_powergate_switch; logic external_subsystem_powergate_switch_ack; - cgra_x_heep_top #( + heepsilon_top #( .COREV_PULP(COREV_PULP), .FPU(FPU), .ZFINX(ZFINX), .X_EXT(X_EXT) - ) cgra_x_heep_top_i ( + ) heepsilon_top_i ( .clk_i, .rst_ni, .boot_select_i, @@ -103,10 +104,10 @@ module testharness #( logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] delayed_tb_external_subsystem_powergate_switch_ack; always_ff @(negedge clk_i) begin - tb_cpu_subsystem_powergate_switch_ack[0] <= cgra_x_heep_top_i.x_heep_system_i.cpu_subsystem_powergate_switch_n; - tb_peripheral_subsystem_powergate_switch_ack[0] <= cgra_x_heep_top_i.x_heep_system_i.peripheral_subsystem_powergate_switch_n; - tb_memory_subsystem_banks_powergate_switch_ack[0] <= cgra_x_heep_top_i.x_heep_system_i.memory_subsystem_banks_powergate_switch_n; - tb_external_subsystem_powergate_switch_ack[0] <= cgra_x_heep_top_i.external_subsystem_powergate_switch; + tb_cpu_subsystem_powergate_switch_ack[0] <= heepsilon_top_i.x_heep_system_i.cpu_subsystem_powergate_switch_n; + tb_peripheral_subsystem_powergate_switch_ack[0] <= heepsilon_top_i.x_heep_system_i.peripheral_subsystem_powergate_switch_n; + tb_memory_subsystem_banks_powergate_switch_ack[0] <= heepsilon_top_i.x_heep_system_i.memory_subsystem_banks_powergate_switch_n; + tb_external_subsystem_powergate_switch_ack[0] <= heepsilon_top_i.external_subsystem_powergate_switch; for (int i = 0; i < SWITCH_ACK_LATENCY; i++) begin tb_memory_subsystem_banks_powergate_switch_ack[i+1] <= tb_memory_subsystem_banks_powergate_switch_ack[i]; tb_cpu_subsystem_powergate_switch_ack[i+1] <= tb_cpu_subsystem_powergate_switch_ack[i]; @@ -122,15 +123,15 @@ module testharness #( always_comb begin `ifndef VERILATOR - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.cpu_subsystem_powergate_switch_ack_i = delayed_tb_cpu_subsystem_powergate_switch_ack; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.peripheral_subsystem_powergate_switch_ack_i = delayed_tb_peripheral_subsystem_powergate_switch_ack; - force cgra_x_heep_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_ack_i = delayed_tb_memory_subsystem_banks_powergate_switch_ack; - force cgra_x_heep_top_i.external_subsystem_powergate_switch_ack = delayed_tb_external_subsystem_powergate_switch_ack; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.cpu_subsystem_powergate_switch_ack_i = delayed_tb_cpu_subsystem_powergate_switch_ack; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.peripheral_subsystem_powergate_switch_ack_i = delayed_tb_peripheral_subsystem_powergate_switch_ack; + force heepsilon_top_i.x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_ack_i = delayed_tb_memory_subsystem_banks_powergate_switch_ack; + force heepsilon_top_i.external_subsystem_powergate_switch_ack = delayed_tb_external_subsystem_powergate_switch_ack; `else - cgra_x_heep_top_i.x_heep_system_i.cpu_subsystem_powergate_switch_ack_n = delayed_tb_cpu_subsystem_powergate_switch_ack; - cgra_x_heep_top_i.x_heep_system_i.peripheral_subsystem_powergate_switch_ack_n = delayed_tb_peripheral_subsystem_powergate_switch_ack; - cgra_x_heep_top_i.x_heep_system_i.memory_subsystem_banks_powergate_switch_ack_n = delayed_tb_memory_subsystem_banks_powergate_switch_ack; - cgra_x_heep_top_i.external_subsystem_powergate_switch_ack = delayed_tb_external_subsystem_powergate_switch_ack; + heepsilon_top_i.x_heep_system_i.cpu_subsystem_powergate_switch_ack_n = delayed_tb_cpu_subsystem_powergate_switch_ack; + heepsilon_top_i.x_heep_system_i.peripheral_subsystem_powergate_switch_ack_n = delayed_tb_peripheral_subsystem_powergate_switch_ack; + heepsilon_top_i.x_heep_system_i.memory_subsystem_banks_powergate_switch_ack_n = delayed_tb_memory_subsystem_banks_powergate_switch_ack; + heepsilon_top_i.external_subsystem_powergate_switch_ack = delayed_tb_external_subsystem_powergate_switch_ack; `endif end