From 432fb07b496eb2217191a1ede6c0253060b34566 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Denkinger?= Date: Tue, 28 Nov 2023 13:53:21 +0100 Subject: [PATCH] Few remaining old name changed. --- Makefile | 18 +++++++++--------- heepsilon.core | 4 ++-- tb/testharness.sv | 15 ++++++++++----- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/Makefile b/Makefile index 9c6f70c5..c06f9c29 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 -# Makefile to generates cgra-x-heep files and build the design with fusesoc +# Makefile to generates heepsilon files and build the design with fusesoc .PHONY: clean help @@ -34,7 +34,7 @@ heepsilon-gen: bash -c "cd hw/vendor/esl_epfl_cgra/data; source cgra_reg_gen.sh; cd ../../../.." # Generates mcu files. First the mcu-gen from X-HEEP is called. -# This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from CGRA-X-HEEP, not the one from X-HEEP. +# This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from heepsilon, not the one from X-HEEP. mcu-gen: heepsilon-gen $(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=${MEMORY_BANKS} $(MAKECMDGOALS) cd hw/vendor/esl_epfl_x_heep &&\ @@ -44,7 +44,7 @@ mcu-gen: heepsilon-gen ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2 ## @param FUSESOC_FLAGS=--flag= vivado-fpga: |venv - fusesoc --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildvivado.log + fusesoc --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildvivado.log # Runs verible formating @@ -53,16 +53,16 @@ verible: # Simulation verilator-sim: - fusesoc --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log + fusesoc --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log questasim-sim: - fusesoc --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log + fusesoc --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log questasim-sim-opt: questasim-sim - $(MAKE) -C build/eslepfl_systems_cgra-x-heep_0/sim-modelsim opt + $(MAKE) -C build/eslepfl_systems_heepsilon_0/sim-modelsim opt vcs-sim: - fusesoc --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log + fusesoc --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log ## Generates the build output for a given application @@ -70,7 +70,7 @@ vcs-sim: ## UART Dumping in uart0.log to show recollected results run-verilator: $(MAKE) app PROJECT=$(PROJECT) - cd ./build/eslepfl_systems_cgra-x-heep_0/sim-verilator; \ + cd ./build/eslepfl_systems_heepsilon_0/sim-verilator; \ ./Vtestharness +firmware=../../../sw/build/main.hex; \ cat uart0.log; \ cd ../../..; @@ -80,7 +80,7 @@ run-verilator: ## UART Dumping in uart0.log to show recollected results run-questasim: $(MAKE) app PROJECT=$(PROJECT) - cd ./build/eslepfl_systems_cgra-x-heep_0/sim-modelsim; \ + cd ./build/eslepfl_systems_heepsilon_0/sim-modelsim; \ make run PLUSARGS="c firmware=../../../sw/build/main.hex"; \ cat uart0.log; \ cd ../../..; diff --git a/heepsilon.core b/heepsilon.core index 456d4b16..a510aeed 100644 --- a/heepsilon.core +++ b/heepsilon.core @@ -4,8 +4,8 @@ CAPI=2: # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -name: eslepfl:systems:cgra-x-heep -description: CGRA X-HEEP Top. +name: eslepfl:systems:heepsilon +description: HEEPsilon (X-HEEP + CGRA) Top. filesets: files_rtl_generic: diff --git a/tb/testharness.sv b/tb/testharness.sv index 287ba6ac..52aae149 100644 --- a/tb/testharness.sv +++ b/tb/testharness.sv @@ -33,6 +33,8 @@ module testharness #( localparam SWITCH_ACK_LATENCY = 15; + localparam EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS; + wire uart_rx; wire uart_tx; logic sim_jtag_enable = (JTAG_DPI == 1); @@ -53,8 +55,12 @@ module testharness #( wire spi_sck; // External subsystems - logic external_subsystem_powergate_switch; - logic external_subsystem_powergate_switch_ack; + logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_n; + logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_ack_n; +// logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_iso_n; +// logic [EXT_DOMAINS_RND-1:0] external_subsystem_rst_n; +// logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_n; +// logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_n; heepsilon_top #( .COREV_PULP(COREV_PULP), @@ -93,9 +99,8 @@ module testharness #( ); //pretending to be SWITCH CELLs that delay by SWITCH_ACK_LATENCY cycles the ACK signal - logic - tb_cpu_subsystem_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1], - tb_peripheral_subsystem_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1]; + logic tb_cpu_subsystem_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1]; + logic tb_peripheral_subsystem_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1]; logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] tb_memory_subsystem_banks_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1]; logic [EXT_DOMAINS_RND-1:0] tb_external_subsystem_powergate_switch_ack_n[SWITCH_ACK_LATENCY+1];