From 418fca3583675a308a82e1043a5b11a7821e8c07 Mon Sep 17 00:00:00 2001 From: Adeeb Shihadeh Date: Sun, 24 Mar 2024 12:10:37 -0700 Subject: [PATCH] enable misra-config checks (#1879) * mostly done * fix rest of misra-config * do other two in next pr --- board/boards/tres.h | 2 +- board/drivers/bxcan.h | 6 +- board/drivers/clock_source.h | 4 +- board/drivers/fake_siren.h | 6 +- board/drivers/fdcan.h | 14 ++-- board/drivers/interrupts.h | 2 +- board/drivers/spi.h | 2 +- board/drivers/usb.h | 136 ++++++++++++++++----------------- board/main.c | 4 +- board/safety/safety_chrysler.h | 5 +- board/safety/safety_gm.h | 6 +- board/safety/safety_honda.h | 3 +- board/stm32f4/clock.h | 4 +- board/stm32f4/lluart.h | 4 +- board/stm32f4/llusb.h | 4 +- board/stm32h7/clock.h | 8 +- board/stm32h7/lladc.h | 8 +- board/stm32h7/llfdcan.h | 8 +- board/stm32h7/lli2c.h | 10 +-- board/stm32h7/llspi.h | 2 +- board/stm32h7/lluart.h | 2 +- board/stm32h7/llusb.h | 2 +- tests/misra/suppressions.txt | 9 ++- tests/misra/test_misra.sh | 14 ++-- 24 files changed, 139 insertions(+), 126 deletions(-) diff --git a/board/boards/tres.h b/board/boards/tres.h index 50d55e280e..14a02bea70 100644 --- a/board/boards/tres.h +++ b/board/boards/tres.h @@ -33,7 +33,7 @@ void tres_init(void) { // Enable USB 3.3V LDO for USB block register_set_bits(&(PWR->CR3), PWR_CR3_USBREGEN); register_set_bits(&(PWR->CR3), PWR_CR3_USB33DEN); - while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0); + while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0U); red_chiplet_init(); diff --git a/board/drivers/bxcan.h b/board/drivers/bxcan.h index ea2705d9d0..27ffcee525 100644 --- a/board/drivers/bxcan.h +++ b/board/drivers/bxcan.h @@ -48,7 +48,7 @@ void update_can_health_pkt(uint8_t can_number, uint32_t ir_reg) { can_health[can_number].total_error_cnt += 1U; // RX message lost due to FIFO overrun - if ((CANx->RF0R & (CAN_RF0R_FOVR0)) != 0) { + if ((CANx->RF0R & (CAN_RF0R_FOVR0)) != 0U) { can_health[can_number].total_rx_lost_cnt += 1U; CANx->RF0R &= ~(CAN_RF0R_FOVR0); } @@ -74,7 +74,7 @@ void process_can(uint8_t can_number) { // check for empty mailbox CANPacket_t to_send; - if ((CANx->TSR & (CAN_TSR_TERR0 | CAN_TSR_ALST0)) != 0) { // last TX failed due to error arbitration lost + if ((CANx->TSR & (CAN_TSR_TERR0 | CAN_TSR_ALST0)) != 0U) { // last TX failed due to error arbitration lost can_health[can_number].total_tx_lost_cnt += 1U; CANx->TSR |= (CAN_TSR_TERR0 | CAN_TSR_ALST0); } @@ -129,7 +129,7 @@ void can_rx(uint8_t can_number) { CAN_TypeDef *CANx = CANIF_FROM_CAN_NUM(can_number); uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number); - while ((CANx->RF0R & CAN_RF0R_FMP0) != 0) { + while ((CANx->RF0R & CAN_RF0R_FMP0) != 0U) { can_health[can_number].total_rx_cnt += 1U; // can is live diff --git a/board/drivers/clock_source.h b/board/drivers/clock_source.h index 11b2fa3247..5d6fdc8a77 100644 --- a/board/drivers/clock_source.h +++ b/board/drivers/clock_source.h @@ -26,8 +26,8 @@ void clock_source_init(void) { set_gpio_alternate(GPIOB, 15, GPIO_AF1_TIM1); // Set PWM mode - register_set(&(TIM1->CCMR1), (0b110 << TIM_CCMR1_OC2M_Pos), 0xFFFFU); - register_set(&(TIM1->CCMR2), (0b110 << TIM_CCMR2_OC3M_Pos), 0xFFFFU); + register_set(&(TIM1->CCMR1), (0b110UL << TIM_CCMR1_OC2M_Pos), 0xFFFFU); + register_set(&(TIM1->CCMR2), (0b110UL << TIM_CCMR2_OC3M_Pos), 0xFFFFU); // Enable output register_set(&(TIM1->BDTR), TIM_BDTR_MOE, 0xFFFFU); diff --git a/board/drivers/fake_siren.h b/board/drivers/fake_siren.h index 38c87deb0c..7c73be0b1c 100644 --- a/board/drivers/fake_siren.h +++ b/board/drivers/fake_siren.h @@ -59,13 +59,13 @@ void fake_siren_init(void) { register_set(&DMA1_Stream1->PAR, (uint32_t) &(DAC1->DHR8R1), 0xFFFFFFFFU); DMA1_Stream1->NDTR = sizeof(fake_siren_lut); register_set(&DMA1_Stream1->FCR, 0U, 0x00000083U); - DMA1_Stream1->CR = (0b11 << DMA_SxCR_PL_Pos); - DMA1_Stream1->CR |= DMA_SxCR_MINC | DMA_SxCR_CIRC | (1 << DMA_SxCR_DIR_Pos); + DMA1_Stream1->CR = (0b11UL << DMA_SxCR_PL_Pos); + DMA1_Stream1->CR |= DMA_SxCR_MINC | DMA_SxCR_CIRC | (1U << DMA_SxCR_DIR_Pos); // Init trigger timer (around 2.5kHz) register_set(&TIM7->PSC, 0U, 0xFFFFU); register_set(&TIM7->ARR, 133U, 0xFFFFU); - register_set(&TIM7->CR2, (0b10 << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk); + register_set(&TIM7->CR2, (0b10U << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk); register_set(&TIM7->CR1, TIM_CR1_ARPE | TIM_CR1_URS, 0x088EU); TIM7->SR = 0U; TIM7->CR1 |= TIM_CR1_CEN; diff --git a/board/drivers/fdcan.h b/board/drivers/fdcan.h index 9e2e0df7f0..0ba228a9e6 100644 --- a/board/drivers/fdcan.h +++ b/board/drivers/fdcan.h @@ -67,14 +67,14 @@ void update_can_health_pkt(uint8_t can_number, uint32_t ir_reg) { FDCANx->IR |= (FDCAN_IR_PED | FDCAN_IR_PEA | FDCAN_IR_EP | FDCAN_IR_BO | FDCAN_IR_RF0L); can_health[can_number].total_error_cnt += 1U; // Check for RX FIFO overflow - if ((ir_reg & (FDCAN_IR_RF0L)) != 0) { + if ((ir_reg & (FDCAN_IR_RF0L)) != 0U) { can_health[can_number].total_rx_lost_cnt += 1U; } // Cases: // 1. while multiplexing between buses 1 and 3 we are getting ACK errors that overwhelm CAN core, by resetting it recovers faster // 2. H7 gets stuck in bus off recovery state indefinitely if ((((can_health[can_number].last_error == CAN_ACK_ERROR) || (can_health[can_number].last_data_error == CAN_ACK_ERROR)) && (can_health[can_number].transmit_error_cnt > 127U)) || - ((ir_reg & FDCAN_IR_BO) != 0)) { + ((ir_reg & FDCAN_IR_BO) != 0U)) { can_health[can_number].can_core_reset_cnt += 1U; can_health[can_number].total_tx_lost_cnt += (FDCAN_TX_FIFO_EL_CNT - (FDCANx->TXFQS & FDCAN_TXFQS_TFFL)); // TX FIFO msgs will be lost after reset llcan_clear_send(FDCANx); @@ -93,7 +93,7 @@ void process_can(uint8_t can_number) { FDCANx->IR |= FDCAN_IR_TFE; // Clear Tx FIFO Empty flag - if ((FDCANx->TXFQS & FDCAN_TXFQS_TFQF) == 0) { + if ((FDCANx->TXFQS & FDCAN_TXFQS_TFQF) == 0U) { CANPacket_t to_send; if (can_pop(can_queues[bus_number], &to_send)) { if (can_check_checksum(&to_send)) { @@ -101,7 +101,7 @@ void process_can(uint8_t can_number) { uint32_t TxFIFOSA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET) + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE); // get the index of the next TX FIFO element (0 to FDCAN_TX_FIFO_EL_CNT - 1) - uint32_t tx_index = (FDCANx->TXFQS >> FDCAN_TXFQS_TFQPI_Pos) & 0x1F; + uint32_t tx_index = (FDCANx->TXFQS >> FDCAN_TXFQS_TFQPI_Pos) & 0x1FU; // only send if we have received a packet canfd_fifo *fifo; fifo = (canfd_fifo *)(TxFIFOSA + (tx_index * FDCAN_TX_FIFO_EL_SIZE)); @@ -153,14 +153,14 @@ void can_rx(uint8_t can_number) { // Clear all new messages from Rx FIFO 0 FDCANx->IR |= FDCAN_IR_RF0N; - while((FDCANx->RXF0S & FDCAN_RXF0S_F0FL) != 0) { + while((FDCANx->RXF0S & FDCAN_RXF0S_F0FL) != 0U) { can_health[can_number].total_rx_cnt += 1U; // can is live pending_can_live = 1; // get the index of the next RX FIFO element (0 to FDCAN_RX_FIFO_0_EL_CNT - 1) - uint32_t rx_fifo_idx = (uint8_t)((FDCANx->RXF0S >> FDCAN_RXF0S_F0GI_Pos) & 0x3F); + uint32_t rx_fifo_idx = (uint8_t)((FDCANx->RXF0S >> FDCAN_RXF0S_F0GI_Pos) & 0x3FU); // Recommended to offset get index by at least +1 if RX FIFO is in overwrite mode and full (datasheet) if((FDCANx->RXF0S & FDCAN_RXF0S_F0F) == FDCAN_RXF0S_F0F) { @@ -232,7 +232,7 @@ void can_rx(uint8_t can_number) { } // Error handling - if ((ir_reg & (FDCAN_IR_PED | FDCAN_IR_PEA | FDCAN_IR_EP | FDCAN_IR_BO | FDCAN_IR_RF0L)) != 0) { + if ((ir_reg & (FDCAN_IR_PED | FDCAN_IR_PEA | FDCAN_IR_EP | FDCAN_IR_BO | FDCAN_IR_RF0L)) != 0U) { update_can_health_pkt(can_number, ir_reg); } } diff --git a/board/drivers/interrupts.h b/board/drivers/interrupts.h index d4c72be1df..77988f6e45 100644 --- a/board/drivers/interrupts.h +++ b/board/drivers/interrupts.h @@ -64,7 +64,7 @@ void handle_interrupt(IRQn_Type irq_type){ // Every second void interrupt_timer_handler(void) { - if (INTERRUPT_TIMER->SR != 0) { + if (INTERRUPT_TIMER->SR != 0U) { for (uint16_t i = 0U; i < NUM_INTERRUPTS; i++) { // Log IRQ call rate faults if (check_interrupt_rate && (interrupts[i].call_counter > interrupts[i].max_call_rate)) { diff --git a/board/drivers/spi.h b/board/drivers/spi.h index efccfc98cc..e1ae010f73 100644 --- a/board/drivers/spi.h +++ b/board/drivers/spi.h @@ -230,7 +230,7 @@ void spi_rx_done(void) { llspi_miso_dma(spi_buf_tx, response_len); spi_state = next_rx_state; - if (!checksum_valid && (spi_checksum_error_count < __UINT16_MAX__)) { + if (!checksum_valid && (spi_checksum_error_count < UINT16_MAX)) { spi_checksum_error_count += 1U; } } diff --git a/board/drivers/usb.h b/board/drivers/usb.h index 9ed500f81a..ddd6b29c38 100644 --- a/board/drivers/usb.h +++ b/board/drivers/usb.h @@ -367,7 +367,7 @@ void *USB_ReadPacket(void *dest, uint16_t len) { uint32_t count32b = ((uint32_t)len + 3U) / 4U; for (uint32_t i = 0; i < count32b; i++) { - *dest_copy = USBx_DFIFO(0); + *dest_copy = USBx_DFIFO(0U); dest_copy++; } return ((void *)dest_copy); @@ -414,7 +414,7 @@ void USB_WritePacket_EP0(uint8_t *src, uint16_t len) { ep0_txlen = len - wplen; USBx_DEVICE->DIEPEMPMSK |= 1; } else { - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; } } @@ -431,8 +431,8 @@ void usb_reset(void) { USBx_DEVICE->DOEPMSK = 0xFFFFFFFFU; // clear interrupts - USBx_INEP(0)->DIEPINT = 0xFF; - USBx_OUTEP(0)->DOEPINT = 0xFF; + USBx_INEP(0U)->DIEPINT = 0xFF; + USBx_OUTEP(0U)->DOEPINT = 0xFF; // unset the address USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; @@ -458,7 +458,7 @@ void usb_reset(void) { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; // ready to receive setup packets - USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (3U << 3); + USBx_OUTEP(0U)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (3U << 3); } char to_hex_char(uint8_t a) { @@ -485,26 +485,26 @@ void usb_setup(void) { switch (setup.b.bRequest) { case USB_REQ_SET_CONFIGURATION: // enable other endpoints, has to be here? - USBx_INEP(1)->DIEPCTL = (0x40U & USB_OTG_DIEPCTL_MPSIZ) | (2UL << 18) | (1UL << 22) | + USBx_INEP(1U)->DIEPCTL = (0x40U & USB_OTG_DIEPCTL_MPSIZ) | (2UL << 18) | (1UL << 22) | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_USBAEP; - USBx_INEP(1)->DIEPINT = 0xFF; + USBx_INEP(1U)->DIEPINT = 0xFF; - USBx_OUTEP(2)->DOEPTSIZ = (1UL << 19) | 0x40U; - USBx_OUTEP(2)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) | + USBx_OUTEP(2U)->DOEPTSIZ = (1UL << 19) | 0x40U; + USBx_OUTEP(2U)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; - USBx_OUTEP(2)->DOEPINT = 0xFF; + USBx_OUTEP(2U)->DOEPINT = 0xFF; - USBx_OUTEP(3)->DOEPTSIZ = (32UL << 19) | 0x800U; - USBx_OUTEP(3)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) | + USBx_OUTEP(3U)->DOEPTSIZ = (32UL << 19) | 0x800U; + USBx_OUTEP(3U)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2UL << 18) | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; - USBx_OUTEP(3)->DOEPINT = 0xFF; + USBx_OUTEP(3U)->DOEPINT = 0xFF; // mark ready to receive - USBx_OUTEP(2)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; - USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(2U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(3U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; USB_WritePacket(0, 0, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_REQ_SET_ADDRESS: // set now? @@ -515,7 +515,7 @@ void usb_setup(void) { #endif USB_WritePacket(0, 0, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_REQ_GET_DESCRIPTOR: @@ -527,17 +527,17 @@ void usb_setup(void) { device_desc[13] = hw_type; // setup transfer USB_WritePacket(device_desc, MIN(sizeof(device_desc), setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; //print("D"); break; case USB_DESC_TYPE_CONFIGURATION: USB_WritePacket(configuration_desc, MIN(sizeof(configuration_desc), setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_DESC_TYPE_DEVICE_QUALIFIER: USB_WritePacket(device_qualifier, MIN(sizeof(device_qualifier), setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_DESC_TYPE_STRING: switch (setup.b.wValue.bw.msb) { @@ -576,16 +576,16 @@ void usb_setup(void) { USB_WritePacket(0, 0, 0); break; } - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_DESC_TYPE_BINARY_OBJECT_STORE: USB_WritePacket(binary_object_store_desc, MIN(sizeof(binary_object_store_desc), setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; default: // nothing here? USB_WritePacket(0, 0, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; } break; @@ -594,24 +594,24 @@ void usb_setup(void) { response[0] = 0; response[1] = 0; USB_WritePacket((void*)&response, 2, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case USB_REQ_SET_INTERFACE: // Store the alt setting number for IN EP behavior. current_int0_alt_setting = setup.b.wValue.w; USB_WritePacket(0, 0, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; case WEBUSB_VENDOR_CODE: switch (setup.b.wIndex.w) { case WEBUSB_REQ_GET_URL: USB_WritePacket(webusb_url_descriptor, MIN(sizeof(webusb_url_descriptor), setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; default: // probably asking for allowed origins, which was removed from the spec USB_WritePacket(0, 0, 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; break; } break; @@ -643,7 +643,7 @@ void usb_setup(void) { // response pending if -1 was returned if (resp_len != -1) { USB_WritePacket(response, MIN(resp_len, setup.b.wLength.w), 0); - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; } } } @@ -671,23 +671,23 @@ void usb_irqhandler(void) { print(" USB interrupt!\n"); #endif - if ((gintsts & USB_OTG_GINTSTS_CIDSCHG) != 0) { + if ((gintsts & USB_OTG_GINTSTS_CIDSCHG) != 0U) { print("connector ID status change\n"); } - if ((gintsts & USB_OTG_GINTSTS_USBRST) != 0) { + if ((gintsts & USB_OTG_GINTSTS_USBRST) != 0U) { print("USB reset\n"); usb_reset(); } - if ((gintsts & USB_OTG_GINTSTS_ENUMDNE) != 0) { + if ((gintsts & USB_OTG_GINTSTS_ENUMDNE) != 0U) { print("enumeration done"); // Full speed, ENUMSPD //puth(USBx_DEVICE->DSTS); print("\n"); } - if ((gintsts & USB_OTG_GINTSTS_OTGINT) != 0) { + if ((gintsts & USB_OTG_GINTSTS_OTGINT) != 0U) { print("OTG int:"); puth(USBx->GOTGINT); print("\n"); @@ -697,7 +697,7 @@ void usb_irqhandler(void) { } // RX FIFO first - if ((gintsts & USB_OTG_GINTSTS_RXFLVL) != 0) { + if ((gintsts & USB_OTG_GINTSTS_RXFLVL) != 0U) { // 1. Read the Receive status pop register volatile unsigned int rxst = USBx->GRXSTSP; int status = (rxst & USB_OTG_GRXSTSP_PKTSTS) >> 17; @@ -763,7 +763,7 @@ void usb_irqhandler(void) { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK | USB_OTG_DCTL_CGINAK; } - if ((gintsts & USB_OTG_GINTSTS_SRQINT) != 0) { + if ((gintsts & USB_OTG_GINTSTS_SRQINT) != 0U) { // we want to do "A-device host negotiation protocol" since we are the A-device /*print("start request\n"); puth(USBx->GOTGCTL); @@ -774,76 +774,76 @@ void usb_irqhandler(void) { } // out endpoint hit - if ((gintsts & USB_OTG_GINTSTS_OEPINT) != 0) { + if ((gintsts & USB_OTG_GINTSTS_OEPINT) != 0U) { #ifdef DEBUG_USB print(" 0:"); - puth(USBx_OUTEP(0)->DOEPINT); + puth(USBx_OUTEP(0U)->DOEPINT); print(" 2:"); - puth(USBx_OUTEP(2)->DOEPINT); + puth(USBx_OUTEP(2U)->DOEPINT); print(" 3:"); - puth(USBx_OUTEP(3)->DOEPINT); + puth(USBx_OUTEP(3U)->DOEPINT); print(" "); - puth(USBx_OUTEP(3)->DOEPCTL); + puth(USBx_OUTEP(3U)->DOEPCTL); print(" 4:"); puth(USBx_OUTEP(4)->DOEPINT); print(" OUT ENDPOINT\n"); #endif - if ((USBx_OUTEP(2)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0) { + if ((USBx_OUTEP(2U)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0U) { #ifdef DEBUG_USB print(" OUT2 PACKET XFRC\n"); #endif - USBx_OUTEP(2)->DOEPTSIZ = (1UL << 19) | 0x40U; - USBx_OUTEP(2)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(2U)->DOEPTSIZ = (1UL << 19) | 0x40U; + USBx_OUTEP(2U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; } - if ((USBx_OUTEP(3)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0) { + if ((USBx_OUTEP(3U)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0U) { #ifdef DEBUG_USB print(" OUT3 PACKET XFRC\n"); #endif // NAK cleared by process_can (if tx buffers have room) outep3_processing = false; refresh_can_tx_slots_available(); - } else if ((USBx_OUTEP(3)->DOEPINT & 0x2000) != 0) { + } else if ((USBx_OUTEP(3U)->DOEPINT & 0x2000U) != 0U) { #ifdef DEBUG_USB print(" OUT3 PACKET WTF\n"); #endif // if NAK was set trigger this, unknown interrupt // TODO: why was this here? fires when TX buffers when we can't clear NAK - // USBx_OUTEP(3)->DOEPTSIZ = (1U << 19) | 0x40U; - // USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; - } else if ((USBx_OUTEP(3)->DOEPINT) != 0) { + // USBx_OUTEP(3U)->DOEPTSIZ = (1U << 19) | 0x40U; + // USBx_OUTEP(3U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + } else if ((USBx_OUTEP(3U)->DOEPINT) != 0U) { #ifdef DEBUG_USB print("OUTEP3 error "); - puth(USBx_OUTEP(3)->DOEPINT); + puth(USBx_OUTEP(3U)->DOEPINT); print("\n"); #endif } else { - // USBx_OUTEP(3)->DOEPINT is 0, ok to skip + // USBx_OUTEP(3U)->DOEPINT is 0, ok to skip } - if ((USBx_OUTEP(0)->DOEPINT & USB_OTG_DIEPINT_XFRC) != 0) { + if ((USBx_OUTEP(0U)->DOEPINT & USB_OTG_DIEPINT_XFRC) != 0U) { // ready for next packet - USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (1U << 3); + USBx_OUTEP(0U)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)) | (1U << 3); } // respond to setup packets - if ((USBx_OUTEP(0)->DOEPINT & USB_OTG_DOEPINT_STUP) != 0) { + if ((USBx_OUTEP(0U)->DOEPINT & USB_OTG_DOEPINT_STUP) != 0U) { usb_setup(); } - USBx_OUTEP(0)->DOEPINT = USBx_OUTEP(0)->DOEPINT; - USBx_OUTEP(2)->DOEPINT = USBx_OUTEP(2)->DOEPINT; - USBx_OUTEP(3)->DOEPINT = USBx_OUTEP(3)->DOEPINT; + USBx_OUTEP(0U)->DOEPINT = USBx_OUTEP(0U)->DOEPINT; + USBx_OUTEP(2U)->DOEPINT = USBx_OUTEP(2U)->DOEPINT; + USBx_OUTEP(3U)->DOEPINT = USBx_OUTEP(3U)->DOEPINT; } // interrupt endpoint hit (Page 1221) - if ((gintsts & USB_OTG_GINTSTS_IEPINT) != 0) { + if ((gintsts & USB_OTG_GINTSTS_IEPINT) != 0U) { #ifdef DEBUG_USB print(" "); - puth(USBx_INEP(0)->DIEPINT); + puth(USBx_INEP(0U)->DIEPINT); print(" "); - puth(USBx_INEP(1)->DIEPINT); + puth(USBx_INEP(1U)->DIEPINT); print(" IN ENDPOINT\n"); #endif @@ -863,7 +863,7 @@ void usb_irqhandler(void) { switch (current_int0_alt_setting) { case 0: ////// Bulk config // *** IN token received when TxFIFO is empty - if ((USBx_INEP(1)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) { + if ((USBx_INEP(1U)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0U) { #ifdef DEBUG_USB print(" IN PACKET QUEUE\n"); #endif @@ -874,7 +874,7 @@ void usb_irqhandler(void) { case 1: ////// Interrupt config // *** IN token received when TxFIFO is empty - if ((USBx_INEP(1)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) { + if ((USBx_INEP(1U)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0U) { #ifdef DEBUG_USB print(" IN PACKET QUEUE\n"); #endif @@ -890,12 +890,12 @@ void usb_irqhandler(void) { break; } - if ((USBx_INEP(0)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) { + if ((USBx_INEP(0U)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0U) { #ifdef DEBUG_USB print(" IN PACKET QUEUE\n"); #endif - if ((ep0_txlen != 0U) && ((USBx_INEP(0)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= 0x40U)) { + if ((ep0_txlen != 0U) && ((USBx_INEP(0U)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= 0x40U)) { uint16_t len = MIN(ep0_txlen, 0x40); USB_WritePacket(ep0_txdata, len, 0); ep0_txdata = &ep0_txdata[len]; @@ -903,14 +903,14 @@ void usb_irqhandler(void) { if (ep0_txlen == 0U) { ep0_txdata = NULL; USBx_DEVICE->DIEPEMPMSK &= ~1; - USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; } } } // clear interrupts - USBx_INEP(0)->DIEPINT = USBx_INEP(0)->DIEPINT; // Why ep0? - USBx_INEP(1)->DIEPINT = USBx_INEP(1)->DIEPINT; + USBx_INEP(0U)->DIEPINT = USBx_INEP(0U)->DIEPINT; // Why ep0? + USBx_INEP(1U)->DIEPINT = USBx_INEP(1U)->DIEPINT; } // clear all interrupts we handled @@ -923,9 +923,9 @@ void usb_irqhandler(void) { void can_tx_comms_resume_usb(void) { ENTER_CRITICAL(); - if (!outep3_processing && (USBx_OUTEP(3)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) != 0) { - USBx_OUTEP(3)->DOEPTSIZ = (32UL << 19) | 0x800U; - USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + if (!outep3_processing && (USBx_OUTEP(3U)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) != 0U) { + USBx_OUTEP(3U)->DOEPTSIZ = (32UL << 19) | 0x800U; + USBx_OUTEP(3U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; } EXIT_CRITICAL(); } diff --git a/board/main.c b/board/main.c index 8e6434e69c..4bd784bf0a 100644 --- a/board/main.c +++ b/board/main.c @@ -145,7 +145,7 @@ void __attribute__ ((noinline)) enable_fpu(void) { uint8_t loop_counter = 0U; uint8_t prev_harness_status = HARNESS_STATUS_NC; void tick_handler(void) { - if (TICK_TIMER->SR != 0) { + if (TICK_TIMER->SR != 0U) { // siren current_board->set_siren((loop_counter & 1U) && (siren_enabled || (siren_countdown > 0U))); @@ -198,7 +198,7 @@ void tick_handler(void) { bootkick_tick(check_started(), recent_heartbeat); // increase heartbeat counter and cap it at the uint32 limit - if (heartbeat_counter < __UINT32_MAX__) { + if (heartbeat_counter < UINT32_MAX) { heartbeat_counter += 1U; } diff --git a/board/safety/safety_chrysler.h b/board/safety/safety_chrysler.h index fa0e1532d5..be27832c9d 100644 --- a/board/safety/safety_chrysler.h +++ b/board/safety/safety_chrysler.h @@ -123,11 +123,12 @@ RxCheck chrysler_ram_hd_rx_checks[] = { const uint32_t CHRYSLER_PARAM_RAM_DT = 1U; // set for Ram DT platform const uint32_t CHRYSLER_PARAM_RAM_HD = 2U; // set for Ram HD platform -enum { +typedef enum { CHRYSLER_RAM_DT, CHRYSLER_RAM_HD, CHRYSLER_PACIFICA, // plus Jeep -} chrysler_platform = CHRYSLER_PACIFICA; +} ChryslerPlatform; +ChryslerPlatform chrysler_platform = CHRYSLER_PACIFICA; const ChryslerAddrs *chrysler_addrs = &CHRYSLER_ADDRS; static uint32_t chrysler_get_checksum(const CANPacket_t *to_push) { diff --git a/board/safety/safety_gm.h b/board/safety/safety_gm.h index 7f8ad72c7e..09ac34ecbd 100644 --- a/board/safety/safety_gm.h +++ b/board/safety/safety_gm.h @@ -59,7 +59,11 @@ enum { GM_BTN_CANCEL = 6, }; -enum {GM_ASCM, GM_CAM} gm_hw = GM_ASCM; +typedef enum { + GM_ASCM, + GM_CAM +} GmHardware; +GmHardware gm_hw = GM_ASCM; bool gm_cam_long = false; bool gm_pcm_cruise = false; diff --git a/board/safety/safety_honda.h b/board/safety/safety_honda.h index 3c93ab9d10..630f6d731c 100644 --- a/board/safety/safety_honda.h +++ b/board/safety/safety_honda.h @@ -79,7 +79,8 @@ bool honda_alt_brake_msg = false; bool honda_fwd_brake = false; bool honda_bosch_long = false; bool honda_bosch_radarless = false; -enum {HONDA_NIDEC, HONDA_BOSCH} honda_hw = HONDA_NIDEC; +typedef enum {HONDA_NIDEC, HONDA_BOSCH} HondaHw; +HondaHw honda_hw = HONDA_NIDEC; int honda_get_pt_bus(void) { diff --git a/board/stm32f4/clock.h b/board/stm32f4/clock.h index 19be574438..f0084faccb 100644 --- a/board/stm32f4/clock.h +++ b/board/stm32f4/clock.h @@ -1,7 +1,7 @@ void clock_init(void) { // enable external oscillator register_set_bits(&(RCC->CR), RCC_CR_HSEON); - while ((RCC->CR & RCC_CR_HSERDY) == 0); + while ((RCC->CR & RCC_CR_HSERDY) == 0U); // divide things // AHB = 96MHz @@ -20,7 +20,7 @@ void clock_init(void) { // start PLL register_set_bits(&(RCC->CR), RCC_CR_PLLON); - while ((RCC->CR & RCC_CR_PLLRDY) == 0); + while ((RCC->CR & RCC_CR_PLLRDY) == 0U); // Configure Flash prefetch, Instruction cache, Data cache and wait state // *** without this, it breaks *** diff --git a/board/stm32f4/lluart.h b/board/stm32f4/lluart.h index ffe7e74da0..64094119f4 100644 --- a/board/stm32f4/lluart.h +++ b/board/stm32f4/lluart.h @@ -5,7 +5,7 @@ void uart_tx_ring(uart_ring *q){ // Send out next byte of TX buffer if (q->w_ptr_tx != q->r_ptr_tx) { // Only send if transmit register is empty (aka last byte has been sent) - if ((q->uart->SR & USART_SR_TXE) != 0) { + if ((q->uart->SR & USART_SR_TXE) != 0U) { q->uart->DR = q->elems_tx[q->r_ptr_tx]; // This clears TXE q->r_ptr_tx = (q->r_ptr_tx + 1U) % q->tx_fifo_size; } @@ -46,7 +46,7 @@ void uart_rx_ring(uart_ring *q){ } void uart_send_break(uart_ring *u) { - while ((u->uart->CR1 & USART_CR1_SBK) != 0); + while ((u->uart->CR1 & USART_CR1_SBK) != 0U); u->uart->CR1 |= USART_CR1_SBK; } diff --git a/board/stm32f4/llusb.h b/board/stm32f4/llusb.h index 20c980864b..6f15c89e11 100644 --- a/board/stm32f4/llusb.h +++ b/board/stm32f4/llusb.h @@ -8,7 +8,7 @@ USB_OTG_GlobalTypeDef *USBx = USB_OTG_FS; #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) #define USBD_FS_TRDT_VALUE 5UL -#define USB_OTG_SPEED_FULL 3 +#define USB_OTG_SPEED_FULL 3UL void usb_irqhandler(void); @@ -27,7 +27,7 @@ void usb_init(void) { // full speed PHY, do reset and remove power down /*puth(USBx->GRSTCTL); print(" resetting PHY\n");*/ - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); //print("AHB idle\n"); // reset PHY here diff --git a/board/stm32h7/clock.h b/board/stm32h7/clock.h index 94e08ca600..2e3ab701d8 100644 --- a/board/stm32h7/clock.h +++ b/board/stm32h7/clock.h @@ -26,17 +26,17 @@ void clock_init(void) { #endif // Set VOS level (VOS3 to 170Mhz, VOS2 to 300Mhz, VOS1 to 400Mhz, VOS0 to 550Mhz) register_set(&(PWR->D3CR), PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0, 0xC000U); //VOS1, needed for 80Mhz CAN FD - while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0); + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U); while ((PWR->CSR1 & PWR_CSR1_ACTVOS) != (PWR->D3CR & PWR_D3CR_VOS)); // check that VOS level was actually set // Configure Flash ACR register LATENCY and WRHIGHFREQ (VOS0 range!) register_set(&(FLASH->ACR), FLASH_ACR_LATENCY_2WS | 0x20U, 0x3FU); // VOS2, AXI 100MHz-150MHz // enable external oscillator HSE register_set_bits(&(RCC->CR), RCC_CR_HSEON); - while ((RCC->CR & RCC_CR_HSERDY) == 0); + while ((RCC->CR & RCC_CR_HSERDY) == 0U); // enable internal HSI48 for USB FS kernel register_set_bits(&(RCC->CR), RCC_CR_HSI48ON); - while ((RCC->CR & RCC_CR_HSI48RDY) == 0); + while ((RCC->CR & RCC_CR_HSI48RDY) == 0U); // Specify the frequency source for PLL1, divider for DIVM1, DIVM2, DIVM3 : HSE, 5, 5, 5 register_set(&(RCC->PLLCKSELR), RCC_PLLCKSELR_PLLSRC_HSE | RCC_PLLCKSELR_DIVM1_0 | RCC_PLLCKSELR_DIVM1_2 | RCC_PLLCKSELR_DIVM2_0 | RCC_PLLCKSELR_DIVM2_2 | RCC_PLLCKSELR_DIVM3_0 | RCC_PLLCKSELR_DIVM3_2, 0x3F3F3F3U); @@ -47,7 +47,7 @@ void clock_init(void) { register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLL1RGE_2 | RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | RCC_PLLCFGR_DIVR1EN, 0x7000CU); // Enable PLL1 register_set_bits(&(RCC->CR), RCC_CR_PLL1ON); - while((RCC->CR & RCC_CR_PLL1RDY) == 0); + while((RCC->CR & RCC_CR_PLL1RDY) == 0U); // *** PLL1 end *** //////////////OTHER CLOCKS//////////////////// diff --git a/board/stm32h7/lladc.h b/board/stm32h7/lladc.h index 01342a4d05..7d818f27af 100644 --- a/board/stm32h7/lladc.h +++ b/board/stm32h7/lladc.h @@ -7,7 +7,7 @@ void adc_init(void) { ADC1->CR &= ~(ADC_CR_ADCALDIF); // Choose single-ended calibration ADC1->CR |= ADC_CR_ADCALLIN; // Lineriality calibration ADC1->CR |= ADC_CR_ADCAL; // Start calibrtation - while((ADC1->CR & ADC_CR_ADCAL) != 0); + while((ADC1->CR & ADC_CR_ADCAL) != 0U); ADC1->ISR |= ADC_ISR_ADRDY; ADC1->CR |= ADC_CR_ADEN; @@ -17,11 +17,11 @@ void adc_init(void) { uint16_t adc_get_raw(uint8_t channel) { uint16_t res = 0U; ADC1->SQR1 &= ~(ADC_SQR1_L); - ADC1->SQR1 = ((uint32_t) channel << 6U); + ADC1->SQR1 = (uint32_t)channel << 6U; - ADC1->SMPR1 = (0x2U << (channel * 3U)); + ADC1->SMPR1 = 0x2UL << (channel * 3UL); ADC1->PCSEL_RES0 = (0x1UL << channel); - ADC1->CFGR2 = (127U << ADC_CFGR2_OVSR_Pos) | (0x7U << ADC_CFGR2_OVSS_Pos) | ADC_CFGR2_ROVSE; + ADC1->CFGR2 = (127UL << ADC_CFGR2_OVSR_Pos) | (0x7U << ADC_CFGR2_OVSS_Pos) | ADC_CFGR2_ROVSE; ADC1->CR |= ADC_CR_ADSTART; while (!(ADC1->ISR & ADC_ISR_EOC)); diff --git a/board/stm32h7/llfdcan.h b/board/stm32h7/llfdcan.h index 4bb6d3d04e..db42024c43 100644 --- a/board/stm32h7/llfdcan.h +++ b/board/stm32h7/llfdcan.h @@ -55,7 +55,7 @@ bool fdcan_request_init(FDCAN_GlobalTypeDef *FDCANx) { // Request init uint32_t timeout_counter = 0U; FDCANx->CCCR |= FDCAN_CCCR_INIT; - while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == 0) { + while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == 0U) { // Delay for about 1ms delay(10000); timeout_counter++; @@ -73,7 +73,7 @@ bool fdcan_exit_init(FDCAN_GlobalTypeDef *FDCANx) { FDCANx->CCCR &= ~(FDCAN_CCCR_INIT); uint32_t timeout_counter = 0U; - while ((FDCANx->CCCR & FDCAN_CCCR_INIT) != 0) { + while ((FDCANx->CCCR & FDCAN_CCCR_INIT) != 0U) { // Delay for about 1ms delay(10000); timeout_counter++; @@ -118,7 +118,7 @@ bool llcan_set_speed(FDCAN_GlobalTypeDef *FDCANx, uint32_t speed, uint32_t data_ uint32_t seg2 = CAN_SEG2(tq, sp); uint8_t sjw = MIN(127U, seg2); - FDCANx->NBTP = (((sjw & 0x7FU)-1U)<NBTP = (((sjw & 0x7FUL)-1U)<DBTP = (((sjw & 0xFU)-1U)<DBTP = (((sjw & 0xFUL)-1U)<CR2, I2C_CR2_ADD10); - I2C->CR2 = ((addr << 1U) & I2C_CR2_SADD_Msk); + I2C->CR2 = ((uint32_t)addr << 1U) & I2C_CR2_SADD_Msk; register_clear_bits(&I2C->CR2, I2C_CR2_RD_WRN); register_set_bits(&I2C->CR2, I2C_CR2_AUTOEND); - I2C->CR2 |= (2 << I2C_CR2_NBYTES_Pos); + I2C->CR2 |= 2UL << I2C_CR2_NBYTES_Pos; I2C->CR2 |= I2C_CR2_START; if(!i2c_status_wait(&I2C->CR2, I2C_CR2_START, 0U)) { @@ -61,10 +61,10 @@ bool i2c_read_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t *value) { bool ret = false; for(uint32_t i=0U; i<10U; i++) { register_clear_bits(&I2C->CR2, I2C_CR2_ADD10); - I2C->CR2 = ((addr << 1U) & I2C_CR2_SADD_Msk); + I2C->CR2 = ((uint32_t)addr << 1U) & I2C_CR2_SADD_Msk; register_clear_bits(&I2C->CR2, I2C_CR2_RD_WRN); register_clear_bits(&I2C->CR2, I2C_CR2_AUTOEND); - I2C->CR2 |= (1 << I2C_CR2_NBYTES_Pos); + I2C->CR2 |= 1UL << I2C_CR2_NBYTES_Pos; I2C->CR2 |= I2C_CR2_START; if(!i2c_status_wait(&I2C->CR2, I2C_CR2_START, 0U)) { @@ -92,7 +92,7 @@ bool i2c_read_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t *value) { I2C->TXDR = reg; // Restart - I2C->CR2 = (((addr << 1) | 0x1U) & I2C_CR2_SADD_Msk) | (1U << I2C_CR2_NBYTES_Pos) | I2C_CR2_RD_WRN | I2C_CR2_START; + I2C->CR2 = (((addr << 1) | 0x1U) & I2C_CR2_SADD_Msk) | (1UL << I2C_CR2_NBYTES_Pos) | I2C_CR2_RD_WRN | I2C_CR2_START; ret = i2c_status_wait(&I2C->CR2, I2C_CR2_START, 0U); if(!ret) { goto end; diff --git a/board/stm32h7/llspi.h b/board/stm32h7/llspi.h index 1947803ac2..903f6a5ecc 100644 --- a/board/stm32h7/llspi.h +++ b/board/stm32h7/llspi.h @@ -71,7 +71,7 @@ void SPI4_IRQ_Handler(void) { // clear flag SPI4->IFCR |= (0x1FFU << 3U); - if (spi_tx_dma_done && ((SPI4->SR & SPI_SR_TXC) != 0)) { + if (spi_tx_dma_done && ((SPI4->SR & SPI_SR_TXC) != 0U)) { spi_tx_dma_done = false; spi_tx_done(false); } diff --git a/board/stm32h7/lluart.h b/board/stm32h7/lluart.h index 0ad7b6a867..6ca6dcec3d 100644 --- a/board/stm32h7/lluart.h +++ b/board/stm32h7/lluart.h @@ -29,7 +29,7 @@ void uart_tx_ring(uart_ring *q){ // Send out next byte of TX buffer if (q->w_ptr_tx != q->r_ptr_tx) { // Only send if transmit register is empty (aka last byte has been sent) - if ((q->uart->ISR & USART_ISR_TXE_TXFNF) != 0) { + if ((q->uart->ISR & USART_ISR_TXE_TXFNF) != 0U) { q->uart->TDR = q->elems_tx[q->r_ptr_tx]; // This clears TXE q->r_ptr_tx = (q->r_ptr_tx + 1U) % q->tx_fifo_size; } diff --git a/board/stm32h7/llusb.h b/board/stm32h7/llusb.h index ada1630f8b..2975f62be6 100644 --- a/board/stm32h7/llusb.h +++ b/board/stm32h7/llusb.h @@ -32,7 +32,7 @@ void usb_init(void) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; delay(250000); // Wait for about 25ms (explicitly stated in H7 ref manual) // Wait for AHB master IDLE state. - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); // Core Soft Reset USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); diff --git a/tests/misra/suppressions.txt b/tests/misra/suppressions.txt index d5b14c836a..b16194e6b9 100644 --- a/tests/misra/suppressions.txt +++ b/tests/misra/suppressions.txt @@ -18,9 +18,12 @@ unusedFunction:*/interrupt_handlers*.h # all of the below suppressions are from new checks introduced after updating # cppcheck from 2.5 -> 2.13. they are listed here to separate the update from # fixing the violations and all are intended to be removed soon after -misra-config -misra-c2012-1.2 # this is from the extensions (e.g. __typeof__) used in the MIN, MAX, ABS, and CLAMP macros -misra-c2012-2.5 +misra-c2012-1.2 # this is from the extensions (e.g. __typeof__) used in the MIN, MAX, ABS, and CLAMP macros +misra-c2012-2.5 # unused macros. a few legit, rest aren't common between F4/H7 builds. should we do this in the unusedFunction pass? misra-c2012-8.7 misra-c2012-8.4 +misra-c2012-11.8 misra-c2012-21.15 + +# FIXME: violations are in ST's F4 headers +misra-c2012-12.2 diff --git a/tests/misra/test_misra.sh b/tests/misra/test_misra.sh index 9fdbea1df7..482eba2414 100755 --- a/tests/misra/test_misra.sh +++ b/tests/misra/test_misra.sh @@ -29,13 +29,17 @@ if [ -z "${SKIP_BUILD}" ]; then fi cppcheck() { + # get all gcc defines: arm-none-eabi-gcc -dM -E - < /dev/null + COMMON_DEFINES="-D__GNUC__=9 -UCMSIS_NVIC_VIRTUAL -UCMSIS_VECTAB_VIRTUAL" + # note that cppcheck build cache results in inconsistent results as of v2.13.0 OUTPUT=$DIR/.output.log - $CPPCHECK_DIR/cppcheck --force --inline-suppr -I $PANDA_DIR/board/ \ - -I $gcc_inc "$(arm-none-eabi-gcc -print-file-name=include)" \ + $CPPCHECK_DIR/cppcheck --inline-suppr -I $PANDA_DIR/board/ \ + -I "$(arm-none-eabi-gcc -print-file-name=include)" \ + -I $PANDA_DIR/board/stm32f4/inc/ -I $PANDA_DIR/board/stm32h7/inc/ \ --suppressions-list=$DIR/suppressions.txt --suppress=*:*inc/* \ --suppress=*:*include/* --error-exitcode=2 --check-level=exhaustive \ - --platform=arm32-wchar_t2 \ + --platform=arm32-wchar_t4 $COMMON_DEFINES \ "$@" |& tee $OUTPUT # cppcheck bug: some MISRA errors won't result in the error exit code, @@ -48,10 +52,10 @@ cppcheck() { PANDA_OPTS="--enable=all --disable=unusedFunction -DPANDA --addon=misra" printf "\n${GREEN}** PANDA F4 CODE **${NC}\n" -cppcheck $PANDA_OPTS -DSTM32F4 -DUID_BASE $PANDA_DIR/board/main.c +cppcheck $PANDA_OPTS -DSTM32F4 -DSTM32F413xx $PANDA_DIR/board/main.c printf "\n${GREEN}** PANDA H7 CODE **${NC}\n" -cppcheck $PANDA_OPTS -DSTM32H7 -DUID_BASE $PANDA_DIR/board/main.c +cppcheck $PANDA_OPTS -DSTM32H7 -DSTM32H725xx $PANDA_DIR/board/main.c # unused needs to run globally #printf "\n${GREEN}** UNUSED ALL CODE **${NC}\n"