fpga_rules.hancho

# FIXME these could stand to be cleaned up a bit.

hancho.base_rules = hancho.repo("{hancho_dir}/base_rules.hancho")

def gen_ivparams(params):
    result = []
    for key, val in params.items():
        if isinstance(val, str):
            # Why Icarus wants string params to have escaped quotes is a mystery.
            val = f"\\\"{val}\\\""
        result.append(f"-P{{top}}.{key}={val}")
    return result

iverilog = hancho.Config(
    desc = "Run iverilog on {rel(in_sv)}",
    command = "iverilog {gen_ivparams(params)} -s{top} -g2012 {defines} {joined_includes} {rel(in_sv)} -o {rel(out_iv)}",
    gen_ivparams = gen_ivparams,
    joined_includes = "{join_prefix('-I', includes)}"
)

verilated_o = hancho(
    hancho.base_rules.compile_cpp,
    in_src  = "/usr/local/share/verilator/include/verilated.cpp",
    out_obj = "verilated.o",
    build_dir = "{build_root}/verilator",
)

verilated_threads_o = hancho(
    hancho.base_rules.compile_cpp,
    in_src  = "/usr/local/share/verilator/include/verilated_threads.cpp",
    out_obj = "verilated_threads.o",
    build_dir = "{build_root}/verilator",
)

def gen_vlparams(c):
    result = []
    for key, val in c.items():
        if isinstance(val, str):
            val = f"\\\"{val}\\\""
        result.append(f"-G{key}={val}")
    return result

verilator_cmd = hancho.Config(
    desc = "Run Verilator on {rel(in_top)}",
    command = "verilator -Wno-width --public {gen_vlparams(params)} {joined_includes} --cc {rel(in_top)} -Mdir {path.dirname(rel(out_makefile))}",
    out_makefile = r"{re.sub(r'([^/\\]+)\.sv', r'V\1.mk', in_top)}",
    out_header   = r"{re.sub(r'([^/\\]+)\.sv', r'V\1.h',  in_top)}",
    joined_includes = "{join_prefix('-I', includes)}",
    gen_vlparams = gen_vlparams,
    params = {},
)

def verilator(hancho, *, in_top, **kwargs):
    verilated = hancho(
        verilator_cmd,
        kwargs,
        in_top = in_top,
    )

    compiled = hancho(
        hancho.base_rules.make,
        kwargs,
        in_makefile = verilated.promise("out_makefile"),
        out_obj = "{swap_ext(in_makefile, '__ALL.o')}",
        flags = [
            "-B",
        ],
    )

    lib = hancho(
        hancho.base_rules.cpp_lib,
        kwargs,
        in_top  = in_top,
        in_objs = [verilated_threads_o, verilated_o, compiled],
        out_lib = "{swap_ext(in_top, '.a')}",
    )

    return hancho(
        command    = None,
        out_lib    = lib.promise("out_lib"),
        out_header = verilated.promise("out_header"),
    )


def gen_chparams(c):
    result = []
    for key, val in c.items():
        if isinstance(val, str):
            val = f"\"{val}\""
        result.append(f"chparam -set {key} {val} {{top}};")
    return result


yosys = hancho.Config(
    desc = "Run yosys on {rel(in_sv)}",
    command = "yosys -q -p 'read_verilog -defer {joined_includes} -sv {rel(in_sv)}; dump; {gen_chparams(params)} synth_ice40 -top {top} -json {rel(out_json)};'",
    out_json = "{swap_ext(in_sv, '.json')}",
    params = {},
    gen_chparams = gen_chparams,
    top = "{stem(in_sv)}",
    joined_includes = "{join_prefix('-I', includes)}",
)


sv2v = hancho.Config(
    desc = "Run sv2v on {rel(in_sv)}",
    command = "sv2v {joined_includes} {rel(in_sv)} -w {rel(out_v)}",
    joined_includes = "{join_prefix('-I', includes)}",
    out_v = "{swap_ext(in_sv, '.v')}",
)

nextpnr = hancho.Config(
    desc    = "Run nextpnr-ice40 on {rel(in_json)}",
    command = "nextpnr-ice40 {flags} -q --json {rel(in_json)} --pcf {pcf} --{chip} --package {package}  --asc {rel(out_asc)}",
    out_asc = "{swap_ext(in_json, '.asc')}",
    flags   = None,
)

icepack = hancho.Config(
    desc    = "Run icepack on {rel(in_asc)}",
    command = "icepack {rel(in_asc)} {rel(out_bin)}",
    out_bin = "{swap_ext(in_asc, '.bin')}",
)

iceprog = hancho.Config(
    desc    = "Run iceprog on {rel(in_bin)}",
    command = "iceprog -S {rel(in_bin)}",
)

# FIXME Remove this and replace with "def synth(hancho, *, ...):"

synth = hancho.Config(
    desc    = "Synth {rel(in_sv)}",
    command = [
        "yosys -p 'read_verilog -defer {joined_includes} -sv {rel(in_sv)}; dump; {chparams(params)} synth_ice40 -json {rel(out_json)};'",
        #"yosys -q -p 'read_verilog -defer {joined_includes} -sv {rel(in_sv)}; dump; {chparams(params)} synth_ice40 -json {rel(out_json)};'",
        "nextpnr-ice40 {flags} -q --json {rel(out_json)} --pcf {pcf} --{chip} --package {package}  --asc {rel(out_asc)}",
        "icepack {rel(out_asc)} {rel(out_bin)}",
    ],
    out_json = "{swap_ext(in_sv, '.json')}",
    out_asc  = "{swap_ext(in_sv, '.asc')}",
    out_bin  = "{swap_ext(in_sv, '.bin')}",
    params   = {},
    chparams = gen_chparams,
    includes = None,
    joined_includes = "{join_prefix('-I', includes)}",
    flags    = None,
)