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board.cpp
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board.cpp
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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2018 Jean-Pierre Charras, jp.charras at wanadoo.fr
* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
* Copyright (C) 2011 Wayne Stambaugh <[email protected]>
*
* Copyright (C) 1992-2024 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <iterator>
#include <wx/log.h>
#include <drc/drc_rtree.h>
#include <board_design_settings.h>
#include <board_commit.h>
#include <board.h>
#include <core/arraydim.h>
#include <core/kicad_algo.h>
#include <connectivity/connectivity_data.h>
#include <convert_shape_list_to_polygon.h>
#include <footprint.h>
#include <font/outline_font.h>
#include <lset.h>
#include <pcb_base_frame.h>
#include <pcb_track.h>
#include <pcb_marker.h>
#include <pcb_group.h>
#include <pcb_generator.h>
#include <pcb_target.h>
#include <pcb_shape.h>
#include <pcb_text.h>
#include <pcb_textbox.h>
#include <pcb_table.h>
#include <pcb_dimension.h>
#include <pgm_base.h>
#include <pcbnew_settings.h>
#include <progress_reporter.h>
#include <project.h>
#include <project/net_settings.h>
#include <project/project_file.h>
#include <project/project_local_settings.h>
#include <ratsnest/ratsnest_data.h>
#include <reporter.h>
#include <tool/tool_manager.h>
#include <tool/selection_conditions.h>
#include <string_utils.h>
#include <core/thread_pool.h>
#include <zone.h>
#include <mutex>
// This is an odd place for this, but CvPcb won't link if it's in board_item.cpp like I first
// tried it.
VECTOR2I BOARD_ITEM::ZeroOffset( 0, 0 );
BOARD::BOARD() :
BOARD_ITEM_CONTAINER( (BOARD_ITEM*) nullptr, PCB_T ),
m_LegacyDesignSettingsLoaded( false ),
m_LegacyCopperEdgeClearanceLoaded( false ),
m_LegacyNetclassesLoaded( false ),
m_boardUse( BOARD_USE::NORMAL ),
m_timeStamp( 1 ),
m_paper( PAGE_INFO::A4 ),
m_project( nullptr ),
m_userUnits( EDA_UNITS::MILLIMETRES ),
m_designSettings( new BOARD_DESIGN_SETTINGS( nullptr, "board.design_settings" ) ),
m_NetInfo( this ),
m_embedFonts( false )
{
// A too small value do not allow connecting 2 shapes (i.e. segments) not exactly connected
// A too large value do not allow safely connecting 2 shapes like very short segments.
m_outlinesChainingEpsilon = pcbIUScale.mmToIU( DEFAULT_CHAINING_EPSILON_MM );
m_DRCMaxClearance = 0;
m_DRCMaxPhysicalClearance = 0;
// we have not loaded a board yet, assume latest until then.
m_fileFormatVersionAtLoad = LEGACY_BOARD_FILE_VERSION;
for( int layer = 0; layer < PCB_LAYER_ID_COUNT; ++layer )
{
m_layers[layer].m_name = GetStandardLayerName( ToLAYER_ID( layer ) );
if( IsCopperLayer( layer ) )
m_layers[layer].m_type = LT_SIGNAL;
else if( layer >= User_1 && layer <= User_9 )
m_layers[layer].m_type = LT_AUX;
else
m_layers[layer].m_type = LT_UNDEFINED;
}
recalcOpposites();
// Creates a zone to show sloder mask bridges created by a min web value
// it it just to show them
m_SolderMaskBridges = new ZONE( this );
m_SolderMaskBridges->SetHatchStyle( ZONE_BORDER_DISPLAY_STYLE::INVISIBLE_BORDER );
m_SolderMaskBridges->SetLayerSet( LSET().set( F_Mask ).set( B_Mask ) );
int infinity = ( std::numeric_limits<int>::max() / 2 ) - pcbIUScale.mmToIU( 1 );
m_SolderMaskBridges->Outline()->NewOutline();
m_SolderMaskBridges->Outline()->Append( VECTOR2I( -infinity, -infinity ) );
m_SolderMaskBridges->Outline()->Append( VECTOR2I( -infinity, +infinity ) );
m_SolderMaskBridges->Outline()->Append( VECTOR2I( +infinity, +infinity ) );
m_SolderMaskBridges->Outline()->Append( VECTOR2I( +infinity, -infinity ) );
m_SolderMaskBridges->SetMinThickness( 0 );
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
// Initialize default netclass.
bds.m_NetSettings->SetDefaultNetclass( std::make_shared<NETCLASS>( NETCLASS::Default ) );
bds.m_NetSettings->GetDefaultNetclass()->SetDescription(
_( "This is the default net class." ) );
bds.UseCustomTrackViaSize( false );
// Initialize ratsnest
m_connectivity.reset( new CONNECTIVITY_DATA() );
// Set flag bits on these that will only be cleared if these are loaded from a legacy file
m_LegacyVisibleLayers.reset().set( Rescue );
m_LegacyVisibleItems.reset().set( GAL_LAYER_INDEX( GAL_LAYER_ID_BITMASK_END ) );
}
BOARD::~BOARD()
{
// Untangle group parents before doing any deleting
for( PCB_GROUP* group : m_groups )
{
for( BOARD_ITEM* item : group->GetItems() )
item->SetParentGroup( nullptr );
}
for( PCB_GENERATOR* generator : m_generators )
{
for( BOARD_ITEM* item : generator->GetItems() )
item->SetParentGroup( nullptr );
}
m_itemByIdCache.clear();
// Clean up the owned elements
DeleteMARKERs();
delete m_SolderMaskBridges;
BOARD_ITEM_SET ownedItems = GetItemSet();
m_zones.clear();
m_footprints.clear();
m_tracks.clear();
m_drawings.clear();
m_groups.clear();
// Generators not currently returned by GetItemSet
for( PCB_GENERATOR* g : m_generators )
ownedItems.insert( g );
m_generators.clear();
// Delete the owned items after clearing the containers, because some item dtors
// cause call chains that query the containers
for( BOARD_ITEM* item : ownedItems )
delete item;
}
bool BOARD::BuildConnectivity( PROGRESS_REPORTER* aReporter )
{
if( !GetConnectivity()->Build( this, aReporter ) )
return false;
UpdateRatsnestExclusions();
return true;
}
void BOARD::SetProject( PROJECT* aProject, bool aReferenceOnly )
{
if( m_project )
ClearProject();
m_project = aProject;
if( aProject && !aReferenceOnly )
{
PROJECT_FILE& project = aProject->GetProjectFile();
// Link the design settings object to the project file
project.m_BoardSettings = &GetDesignSettings();
// Set parent, which also will load the values from JSON stored in the project if we don't
// have legacy design settings loaded already
project.m_BoardSettings->SetParent( &project, !m_LegacyDesignSettingsLoaded );
// The DesignSettings' netclasses pointer will be pointing to its internal netclasses
// list at this point. If we loaded anything into it from a legacy board file then we
// want to transfer it over to the project netclasses list.
if( m_LegacyNetclassesLoaded )
{
std::shared_ptr<NET_SETTINGS> legacySettings = GetDesignSettings().m_NetSettings;
std::shared_ptr<NET_SETTINGS>& projectSettings = project.NetSettings();
projectSettings->SetDefaultNetclass( legacySettings->GetDefaultNetclass() );
projectSettings->SetNetclasses( legacySettings->GetNetclasses() );
projectSettings->SetNetclassPatternAssignments(
std::move( legacySettings->GetNetclassPatternAssignments() ) );
}
// Now update the DesignSettings' netclass pointer to point into the project.
GetDesignSettings().m_NetSettings = project.NetSettings();
}
}
void BOARD::ClearProject()
{
if( !m_project )
return;
PROJECT_FILE& project = m_project->GetProjectFile();
// Owned by the BOARD
if( project.m_BoardSettings )
{
project.ReleaseNestedSettings( project.m_BoardSettings );
project.m_BoardSettings = nullptr;
}
GetDesignSettings().m_NetSettings = nullptr;
GetDesignSettings().SetParent( nullptr );
m_project = nullptr;
}
void BOARD::IncrementTimeStamp()
{
m_timeStamp++;
if( !m_IntersectsAreaCache.empty()
|| !m_EnclosedByAreaCache.empty()
|| !m_IntersectsCourtyardCache.empty()
|| !m_IntersectsFCourtyardCache.empty()
|| !m_IntersectsBCourtyardCache.empty()
|| !m_LayerExpressionCache.empty()
|| !m_ZoneBBoxCache.empty()
|| m_CopperItemRTreeCache
|| m_maxClearanceValue.has_value() )
{
std::unique_lock<std::shared_mutex> writeLock( m_CachesMutex );
m_IntersectsAreaCache.clear();
m_EnclosedByAreaCache.clear();
m_IntersectsCourtyardCache.clear();
m_IntersectsFCourtyardCache.clear();
m_IntersectsBCourtyardCache.clear();
m_LayerExpressionCache.clear();
m_ZoneBBoxCache.clear();
m_CopperItemRTreeCache = nullptr;
// These are always regenerated before use, but still probably safer to clear them
// while we're here.
m_DRCMaxClearance = 0;
m_DRCMaxPhysicalClearance = 0;
m_DRCZones.clear();
m_DRCCopperZones.clear();
m_ZoneIsolatedIslandsMap.clear();
m_CopperZoneRTreeCache.clear();
m_maxClearanceValue.reset();
}
}
void BOARD::UpdateRatsnestExclusions()
{
std::set<std::pair<KIID, KIID>> m_ratsnestExclusions;
for( PCB_MARKER* marker : GetBoard()->Markers() )
{
if( marker->GetMarkerType() == MARKER_BASE::MARKER_RATSNEST && marker->IsExcluded() )
{
const std::shared_ptr<RC_ITEM>& rcItem = marker->GetRCItem();
m_ratsnestExclusions.emplace( rcItem->GetMainItemID(), rcItem->GetAuxItemID() );
m_ratsnestExclusions.emplace( rcItem->GetAuxItemID(), rcItem->GetMainItemID() );
}
}
GetConnectivity()->RunOnUnconnectedEdges(
[&]( CN_EDGE& aEdge )
{
if( aEdge.GetSourceNode() && aEdge.GetTargetNode()
&& !aEdge.GetSourceNode()->Dirty() && !aEdge.GetTargetNode()->Dirty() )
{
std::pair<KIID, KIID> ids = { aEdge.GetSourceNode()->Parent()->m_Uuid,
aEdge.GetTargetNode()->Parent()->m_Uuid };
aEdge.SetVisible( m_ratsnestExclusions.count( ids ) == 0 );
}
return true;
} );
}
void BOARD::RecordDRCExclusions()
{
m_designSettings->m_DrcExclusions.clear();
m_designSettings->m_DrcExclusionComments.clear();
for( PCB_MARKER* marker : m_markers )
{
if( marker->IsExcluded() )
{
wxString serialized = marker->SerializeToString();
m_designSettings->m_DrcExclusions.insert( serialized );
m_designSettings->m_DrcExclusionComments[ serialized ] = marker->GetComment();
}
}
}
std::vector<PCB_MARKER*> BOARD::ResolveDRCExclusions( bool aCreateMarkers )
{
std::set<wxString> exclusions = m_designSettings->m_DrcExclusions;
std::map<wxString, wxString> comments = m_designSettings->m_DrcExclusionComments;
m_designSettings->m_DrcExclusions.clear();
m_designSettings->m_DrcExclusionComments.clear();
for( PCB_MARKER* marker : GetBoard()->Markers() )
{
wxString serialized = marker->SerializeToString();
std::set<wxString>::iterator it = exclusions.find( serialized );
if( it != exclusions.end() )
{
marker->SetExcluded( true, comments[ serialized ] );
// Exclusion still valid; store back to BOARD_DESIGN_SETTINGS
m_designSettings->m_DrcExclusions.insert( serialized );
m_designSettings->m_DrcExclusionComments[ serialized ] = comments[ serialized ];
exclusions.erase( it );
}
}
std::vector<PCB_MARKER*> newMarkers;
if( aCreateMarkers )
{
for( const wxString& serialized : exclusions )
{
PCB_MARKER* marker = PCB_MARKER::DeserializeFromString( serialized );
if( !marker )
continue;
// Check to see if items still exist
for( const KIID& guid : marker->GetRCItem()->GetIDs() )
{
if( GetItem( guid ) == DELETED_BOARD_ITEM::GetInstance() )
{
delete marker;
marker = nullptr;
break;
}
}
if( marker )
{
marker->SetExcluded( true, comments[ serialized ] );
newMarkers.push_back( marker );
// Exclusion still valid; store back to BOARD_DESIGN_SETTINGS
m_designSettings->m_DrcExclusions.insert( serialized );
m_designSettings->m_DrcExclusionComments[ serialized ] = comments[ serialized ];
}
}
}
return newMarkers;
}
void BOARD::GetContextualTextVars( wxArrayString* aVars ) const
{
auto add =
[&]( const wxString& aVar )
{
if( !alg::contains( *aVars, aVar ) )
aVars->push_back( aVar );
};
add( wxT( "LAYER" ) );
add( wxT( "FILENAME" ) );
add( wxT( "FILEPATH" ) );
add( wxT( "PROJECTNAME" ) );
add( wxT( "DRC_ERROR <message_text>" ) );
add( wxT( "DRC_WARNING <message_text>" ) );
GetTitleBlock().GetContextualTextVars( aVars );
if( GetProject() )
{
for( std::pair<wxString, wxString> entry : GetProject()->GetTextVars() )
add( entry.first );
}
}
bool BOARD::ResolveTextVar( wxString* token, int aDepth ) const
{
if( token->Contains( ':' ) )
{
wxString remainder;
wxString ref = token->BeforeFirst( ':', &remainder );
BOARD_ITEM* refItem = GetItem( KIID( ref ) );
if( refItem && refItem->Type() == PCB_FOOTPRINT_T )
{
FOOTPRINT* refFP = static_cast<FOOTPRINT*>( refItem );
if( refFP->ResolveTextVar( &remainder, aDepth + 1 ) )
{
*token = remainder;
return true;
}
}
}
if( token->IsSameAs( wxT( "FILENAME" ) ) )
{
wxFileName fn( GetFileName() );
*token = fn.GetFullName();
return true;
}
else if( token->IsSameAs( wxT( "FILEPATH" ) ) )
{
wxFileName fn( GetFileName() );
*token = fn.GetFullPath();
return true;
}
else if( token->IsSameAs( wxT( "PROJECTNAME" ) ) && GetProject() )
{
*token = GetProject()->GetProjectName();
return true;
}
wxString var = *token;
if( m_properties.count( var ) )
{
*token = m_properties.at( var );
return true;
}
else if( GetTitleBlock().TextVarResolver( token, m_project ) )
{
return true;
}
if( GetProject() && GetProject()->TextVarResolver( token ) )
return true;
return false;
}
VECTOR2I BOARD::GetPosition() const
{
return ZeroOffset;
}
void BOARD::SetPosition( const VECTOR2I& aPos )
{
wxLogWarning( wxT( "This should not be called on the BOARD object") );
}
void BOARD::Move( const VECTOR2I& aMoveVector ) // overload
{
INSPECTOR_FUNC inspector =
[&] ( EDA_ITEM* item, void* testData )
{
if( item->IsBOARD_ITEM() )
{
BOARD_ITEM* board_item = static_cast<BOARD_ITEM*>( item );
// aMoveVector was snapshotted, don't need "data".
// Only move the top level group
if( !board_item->GetParentGroup() && !board_item->GetParentFootprint() )
board_item->Move( aMoveVector );
}
return INSPECT_RESULT::CONTINUE;
};
Visit( inspector, nullptr, GENERAL_COLLECTOR::BoardLevelItems );
}
TRACKS BOARD::TracksInNet( int aNetCode )
{
TRACKS ret;
INSPECTOR_FUNC inspector = [aNetCode, &ret]( EDA_ITEM* item, void* testData )
{
PCB_TRACK* t = static_cast<PCB_TRACK*>( item );
if( t->GetNetCode() == aNetCode )
ret.push_back( t );
return INSPECT_RESULT::CONTINUE;
};
// visit this BOARD's PCB_TRACKs and PCB_VIAs with above TRACK INSPECTOR which
// appends all in aNetCode to ret.
Visit( inspector, nullptr, GENERAL_COLLECTOR::Tracks );
return ret;
}
bool BOARD::SetLayerDescr( PCB_LAYER_ID aIndex, const LAYER& aLayer )
{
if( unsigned( aIndex ) < arrayDim( m_layers ) )
{
m_layers[ aIndex ] = aLayer;
recalcOpposites();
return true;
}
return false;
}
PCB_LAYER_ID BOARD::GetLayerID( const wxString& aLayerName ) const
{
// Check the BOARD physical layer names.
for( int layer = 0; layer < PCB_LAYER_ID_COUNT; ++layer )
{
if ( m_layers[ layer ].m_name == aLayerName || m_layers[ layer ].m_userName == aLayerName )
return ToLAYER_ID( layer );
}
// Otherwise fall back to the system standard layer names for virtual layers.
for( int layer = 0; layer < PCB_LAYER_ID_COUNT; ++layer )
{
if( GetStandardLayerName( ToLAYER_ID( layer ) ) == aLayerName )
return ToLAYER_ID( layer );
}
return UNDEFINED_LAYER;
}
const wxString BOARD::GetLayerName( PCB_LAYER_ID aLayer ) const
{
// All layer names are stored in the BOARD.
if( IsLayerEnabled( aLayer ) )
{
// Standard names were set in BOARD::BOARD() but they may be over-ridden by
// BOARD::SetLayerName(). For copper layers, return the user defined layer name,
// if it was set. Otherwise return the Standard English layer name.
if( !m_layers[aLayer].m_userName.IsEmpty() )
return m_layers[aLayer].m_userName;
}
return GetStandardLayerName( aLayer );
}
bool BOARD::SetLayerName( PCB_LAYER_ID aLayer, const wxString& aLayerName )
{
if( !aLayerName.IsEmpty() )
{
// no quote chars in the name allowed
if( aLayerName.Find( wxChar( '"' ) ) != wxNOT_FOUND )
return false;
if( IsLayerEnabled( aLayer ) )
{
m_layers[aLayer].m_userName = aLayerName;
recalcOpposites();
return true;
}
}
return false;
}
LAYER_T BOARD::GetLayerType( PCB_LAYER_ID aLayer ) const
{
if( IsLayerEnabled( aLayer ) )
return m_layers[aLayer].m_type;
if( aLayer >= User_1 && aLayer <= User_9 )
return LT_AUX;
else if( IsCopperLayer( aLayer ) )
return LT_SIGNAL;
else
return LT_UNDEFINED;
}
bool BOARD::SetLayerType( PCB_LAYER_ID aLayer, LAYER_T aLayerType )
{
if( IsLayerEnabled( aLayer ) )
{
m_layers[aLayer].m_type = aLayerType;
recalcOpposites();
return true;
}
return false;
}
const char* LAYER::ShowType( LAYER_T aType )
{
switch( aType )
{
default:
case LT_SIGNAL: return "signal";
case LT_POWER: return "power";
case LT_MIXED: return "mixed";
case LT_JUMPER: return "jumper";
case LT_AUX: return "auxiliary";
case LT_FRONT: return "front";
case LT_BACK: return "back";
}
}
LAYER_T LAYER::ParseType( const char* aType )
{
if( strcmp( aType, "signal" ) == 0 ) return LT_SIGNAL;
else if( strcmp( aType, "power" ) == 0 ) return LT_POWER;
else if( strcmp( aType, "mixed" ) == 0 ) return LT_MIXED;
else if( strcmp( aType, "jumper" ) == 0 ) return LT_JUMPER;
else if( strcmp( aType, "auxiliary" ) == 0 ) return LT_AUX;
else if( strcmp( aType, "front" ) == 0 ) return LT_FRONT;
else if( strcmp( aType, "back" ) == 0 ) return LT_BACK;
else return LT_UNDEFINED;
}
void BOARD::recalcOpposites()
{
for( int layer = F_Cu; layer < User_9; ++layer )
m_layers[layer].m_opposite = ::FlipLayer( ToLAYER_ID( layer ), GetCopperLayerCount() );
// Match up similary-named front/back user layers
for( int layer = User_1; layer <= User_9; ++layer )
{
if( m_layers[layer].m_opposite != layer ) // already paired
continue;
if( m_layers[layer].m_type != LT_FRONT )
continue;
wxString principalName = m_layers[layer].m_userName.AfterFirst( '.' );
for( int ii = User_1; ii <= User_9; ++ii )
{
if( ii == layer ) // can't pair with self
continue;
if( m_layers[ii].m_opposite != ii ) // already paired
continue;
if( m_layers[ii].m_type != LT_BACK )
continue;
wxString candidate = m_layers[ii].m_userName.AfterFirst( '.' );
if( !candidate.IsEmpty() && candidate == principalName )
{
m_layers[layer].m_opposite = ii;
m_layers[ii].m_opposite = layer;
break;
}
}
}
// Match up non-custom-named consecutive front/back user layer pairs
for( int layer = User_1; layer < User_9; ++layer )
{
int next = layer + 1;
// ignore already-matched layers
if( m_layers[layer].m_opposite != layer || m_layers[next].m_opposite != next )
continue;
// ignore layer pairs that aren't consecutive front/back
if( m_layers[layer].m_type != LT_FRONT || m_layers[next].m_type != LT_BACK )
continue;
if( m_layers[layer].m_userName != m_layers[layer].m_name
&& m_layers[next].m_userName != m_layers[next].m_name )
{
m_layers[layer].m_opposite = next;
m_layers[next].m_opposite = layer;
}
}
}
PCB_LAYER_ID BOARD::FlipLayer( PCB_LAYER_ID aLayer ) const
{
return ToLAYER_ID( m_layers[aLayer].m_opposite );
}
int BOARD::GetCopperLayerCount() const
{
return GetDesignSettings().GetCopperLayerCount();
}
void BOARD::SetCopperLayerCount( int aCount )
{
GetDesignSettings().SetCopperLayerCount( aCount );
}
PCB_LAYER_ID BOARD::GetCopperLayerStackMaxId() const
{
int imax = GetCopperLayerCount();
// layers IDs are F_Cu, B_Cu, and even IDs values (imax values)
if( imax <= 2 ) // at least 2 layers are expected
return B_Cu;
// For a 4 layer, last ID is In2_Cu = 6 (IDs are 0, 2, 4, 6)
return static_cast<PCB_LAYER_ID>( (imax-1) * 2 );
}
int BOARD::LayerDepth( PCB_LAYER_ID aStartLayer, PCB_LAYER_ID aEndLayer ) const
{
if( aStartLayer > aEndLayer )
std::swap( aStartLayer, aEndLayer );
if( aEndLayer == B_Cu )
aEndLayer = ToLAYER_ID( F_Cu + GetCopperLayerCount() - 1 );
return aEndLayer - aStartLayer;
}
LSET BOARD::GetEnabledLayers() const
{
return GetDesignSettings().GetEnabledLayers();
}
bool BOARD::IsLayerVisible( PCB_LAYER_ID aLayer ) const
{
// If there is no project, assume layer is visible always
return GetDesignSettings().IsLayerEnabled( aLayer )
&& ( !m_project || m_project->GetLocalSettings().m_VisibleLayers[aLayer] );
}
LSET BOARD::GetVisibleLayers() const
{
return m_project ? m_project->GetLocalSettings().m_VisibleLayers : LSET::AllLayersMask();
}
void BOARD::SetEnabledLayers( LSET aLayerSet )
{
GetDesignSettings().SetEnabledLayers( aLayerSet );
}
bool BOARD::IsLayerEnabled( PCB_LAYER_ID aLayer ) const
{
return GetDesignSettings().IsLayerEnabled( aLayer );
}
void BOARD::SetVisibleLayers( LSET aLayerSet )
{
if( m_project )
m_project->GetLocalSettings().m_VisibleLayers = aLayerSet;
}
void BOARD::SetVisibleElements( const GAL_SET& aSet )
{
// Call SetElementVisibility for each item
// to ensure specific calculations that can be needed by some items,
// just changing the visibility flags could be not sufficient.
for( size_t i = 0; i < aSet.size(); i++ )
SetElementVisibility( GAL_LAYER_ID_START + static_cast<int>( i ), aSet[i] );
}
void BOARD::SetVisibleAlls()
{
SetVisibleLayers( LSET().set() );
// Call SetElementVisibility for each item,
// to ensure specific calculations that can be needed by some items
for( GAL_LAYER_ID ii = GAL_LAYER_ID_START; ii < GAL_LAYER_ID_BITMASK_END; ++ii )
SetElementVisibility( ii, true );
}
GAL_SET BOARD::GetVisibleElements() const
{
return m_project ? m_project->GetLocalSettings().m_VisibleItems : GAL_SET().set();
}
bool BOARD::IsElementVisible( GAL_LAYER_ID aLayer ) const
{
return !m_project || m_project->GetLocalSettings().m_VisibleItems[aLayer - GAL_LAYER_ID_START];
}
void BOARD::SetElementVisibility( GAL_LAYER_ID aLayer, bool isEnabled )
{
if( m_project )
m_project->GetLocalSettings().m_VisibleItems.set( aLayer - GAL_LAYER_ID_START, isEnabled );
switch( aLayer )
{
case LAYER_RATSNEST:
{
// because we have a tool to show/hide ratsnest relative to a pad or a footprint
// so the hide/show option is a per item selection
for( PCB_TRACK* track : Tracks() )
track->SetLocalRatsnestVisible( isEnabled );
for( FOOTPRINT* footprint : Footprints() )
{
for( PAD* pad : footprint->Pads() )
pad->SetLocalRatsnestVisible( isEnabled );
}
for( ZONE* zone : Zones() )
zone->SetLocalRatsnestVisible( isEnabled );
break;
}
default:
;
}
}
bool BOARD::IsFootprintLayerVisible( PCB_LAYER_ID aLayer ) const
{
switch( aLayer )
{
case F_Cu: return IsElementVisible( LAYER_FOOTPRINTS_FR );
case B_Cu: return IsElementVisible( LAYER_FOOTPRINTS_BK );
default: wxFAIL_MSG( wxT( "BOARD::IsModuleLayerVisible(): bad layer" ) ); return true;
}
}
BOARD_DESIGN_SETTINGS& BOARD::GetDesignSettings() const
{
return *m_designSettings;
}
int BOARD::GetMaxClearanceValue() const
{
if( !m_maxClearanceValue.has_value() )
{
std::unique_lock<std::shared_mutex> writeLock( m_CachesMutex );
int worstClearance = m_designSettings->GetBiggestClearanceValue();
for( ZONE* zone : m_zones )
worstClearance = std::max( worstClearance, zone->GetLocalClearance().value() );
for( FOOTPRINT* footprint : m_footprints )
{
for( PAD* pad : footprint->Pads() )
{
std::optional<int> override = pad->GetClearanceOverrides( nullptr );
if( override.has_value() )
worstClearance = std::max( worstClearance, override.value() );
}
for( ZONE* zone : footprint->Zones() )
worstClearance = std::max( worstClearance, zone->GetLocalClearance().value() );
}
m_maxClearanceValue = worstClearance;
}
return m_maxClearanceValue.value_or( 0 );
};
void BOARD::CacheTriangulation( PROGRESS_REPORTER* aReporter, const std::vector<ZONE*>& aZones )
{
std::vector<ZONE*> zones = aZones;
if( zones.empty() )
zones = m_zones;
if( zones.empty() )
return;
if( aReporter )
aReporter->Report( _( "Tessellating copper zones..." ) );
thread_pool& tp = GetKiCadThreadPool();
std::vector<std::future<size_t>> returns;
returns.reserve( zones.size() );
auto cache_zones = [aReporter]( ZONE* aZone ) -> size_t
{
if( aReporter && aReporter->IsCancelled() )
return 0;
aZone->CacheTriangulation();
if( aReporter )
aReporter->AdvanceProgress();
return 1;
};
for( ZONE* zone : zones )
returns.emplace_back( tp.submit( cache_zones, zone ) );
// Finalize the triangulation threads
for( const std::future<size_t>& ret : returns )
{
std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
while( status != std::future_status::ready )
{
if( aReporter )
aReporter->KeepRefreshing();
status = ret.wait_for( std::chrono::milliseconds( 250 ) );
}
}
}
void BOARD::FixupEmbeddedData()
{
for( FOOTPRINT* footprint : m_footprints )
{
for( auto& [filename, embeddedFile] : footprint->EmbeddedFileMap() )
{
EMBEDDED_FILES::EMBEDDED_FILE* file = GetEmbeddedFile( filename );
if( file )
{
embeddedFile->compressedEncodedData = file->compressedEncodedData;
embeddedFile->decompressedData = file->decompressedData;
embeddedFile->data_hash = file->data_hash;
embeddedFile->is_valid = file->is_valid;
}
}
}
}
void BOARD::Add( BOARD_ITEM* aBoardItem, ADD_MODE aMode, bool aSkipConnectivity )